Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.

Abstract: Detecting buffer-overflow exploits scans generically for shellcode without using virus signatures and maintains close to a zero false-positive rate. Shellcode is detected generically without determining specifically which buffer-overflow exploit is being used. Protection is offered against unknown buffer-overflow exploits. A file is scanned to determine if a vulnerable buffer in that file includes suspect code that has characteristics of shellcode. Next, it is determined if the suspect code contains a routine to find the imagebase of Kernel32.dll using any of the techniques of PEB, TOS or SEH (process environment block, top of stack or structured exception handling). It is next determined if the suspect code contains a routine to search for APIs in the export table of kernel32.dll. Techniques for analyzing the suspect code include static analysis and executing the code in an emulator. A high sensitivity setting determines that shellcode is present when any of the techniques of PEB, TOS or SEH are found.

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.

Abstract: A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.

Abstract: A method of forming measuring targets for measuring the dimensions of a substrate during a substrate manufacturing process is provided. First, a board having a base layer and a conductive layer is provided, wherein the conductive layer is disposed on a surface of the base layer. Then, at least one through hole is formed in the board as a measuring target for measuring the dimensions of the substrate. Next, a plated via is formed in the through hole as another measuring target for measuring the dimensions of the substrate. Thereafter, a patterned dielectric layer is formed on the board to expose the plated via as a next measuring target for measuring the dimensions of the substrate. In the present invention, measuring targets are formed during a substrate manufacturing process and the dimensions of the substrate are measured instantly. The accuracy in process alignment is improved without increasing the fabrication cost.

Abstract: An insulative housing of a PCMCIA card connector includes a header defining a plurality of passageways therein. The passageways are exposed to a rear face of the header for allowing contact elements to be inserted therein from the rear face. The header has a top face forming a post and an opposite bottom face defining a corresponding bore. The post pivotally supports a rocking arm of a card ejection mechanism for releasing a PCMCIA card from the connector. A number of insulative housings may be vertically stacked and precisely positioned with respect to each other by inserting the post of a lower housing into the bore of an upper housing thereby aligning the passageways of the housings. Contact elements fixed to a carrier strip and equally spaced therealong are simultaneously inserted into the passageways of the housings thereby enhancing the efficiency of assembling the PCMCIA card connectors.