Abstract: A radio frequency (RF) device and a voltage generation and harmonic suppressor thereof are provided. The RF device includes the voltage generation and harmonic suppressor and a RF circuit. The voltage generation and harmonic suppressor is configured to receive a RF signal to output at least one direct current (DC) voltage related to the RF signal, and configured to suppress a harmonic generated by the RF signal in the voltage generation and harmonic suppressor. The RF circuit is configured to receive the RF signal, and configured to perform an operation according to the at least one DC voltage.

Abstract: A radio frequency switch has an antenna end, a first signal end for transmitting a first radio frequency signal, a second signal end for transmitting a second radio frequency signal, a third signal end for transmitting a third radio frequency signal, a first series path having a first switch, a second series path having a second switch, a third series path having a third switch, a first shunt path coupled between the first signal end and a node, a second shunt path coupled between the second signal end and the node, a common path coupled between the node and a first reference voltage end, and a third shunt path coupled between the third signal end and a second reference voltage end. The first series path and the second series path are connected to a common ground pad via the common path.

Abstract: A radio frequency switch has an antenna end, a first signal end for transmitting a first radio frequency signal, a second signal end for transmitting a second radio frequency signal, a third signal end for transmitting a third radio frequency signal, a first series path having a first switch, a second series path having a second switch, a third series path having a third switch, a first shunt path coupled between the first signal end and a node, a second shunt path coupled between the second signal end and the node, a common path coupled between the node and a first reference voltage end, and a third shunt path coupled between the third signal end and a second reference voltage end. The first series path and the second series path are connected to a common ground pad via the common path.

Abstract: A radio frequency (RF) device and a voltage generation and harmonic suppressor thereof are provided. The RF device includes the voltage generation and harmonic suppressor and a RF circuit. The voltage generation and harmonic suppressor is configured to receive a RF signal to output at least one direct current (DC) voltage related to the RF signal, and configured to suppress a harmonic generated by the RF signal in the voltage generation and harmonic suppressor. The RF circuit is configured to receive the RF signal, and configured to perform an operation according to the at least one DC voltage.

Abstract: A system, a control method and an apparatus for chemical mechanical polishing (CMP) are introduced in the present application. The CMP apparatus may include a polishing pad, a first sensor, a polishing head and a condition. The polishing pad has a plurality of groves arranged randomly or in a specific pattern. The first sensor is configured to measure the pad profile of the polishing pad, where the pad profile includes the depth of each of the grooves on the polishing pad. The polishing head and the conditioner are operated according to at least one polishing condition, and the at least one polishing condition is tuned according to the pad profile.

Abstract: A system, a control method and an apparatus for chemical mechanical polishing (CMP) are introduced in the present application. The CMP apparatus may include a polishing pad, a first sensor, a polishing head and a condition. The polishing pad has a plurality of groves arranged randomly or in a specific pattern. The first sensor is configured to measure the pad profile of the polishing pad, where the pad profile includes the depth of each of the grooves on the polishing pad. The polishing head and the conditioner are operated according to at least one polishing condition, and the at least one polishing condition is tuned according to the pad profile.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: A method to produce a high-purity Zr-89 on a solid target through physical irradiation and measurement by selecting a target Barn value of the cross-sectional area of nuclear reaction, drawing a horizontal line to intersect at two points on the function diagram curve and drawing a vertical line downward from each of the two points intersecting at X-axis to obtain incident energy values at the two intersecting points on the X-axis, and followed by plotting an attenuation function diagram curve of penetration depth versus incident energy of Y-89(p,n)Zr-89, selecting an attenuation function diagram curve and a minimum attenuation position of the selected attenuation function diagram curve in correspondence to the incident energy in the interval of incident energy absorption range to obtain an optimal plating thickness value on the solid target.

Abstract: A method of synthesizing a compound of imaging agent with HDAC (histone deacetylase) inhibitor consists of two parts, the first part of the method is to provide the inhibitor of HDAC with a compound of imaging agent that includes HDAC inhibitor BNL-26 (C22H23N3O) and its analogs to be labeled with radionuclide F-18, producing a series of new nuclear medicine tracers: BNL-26-CH2CH218F, BNL-26a-CH2CH218FF, BNL-26b-CH2CH218F, BNL-26c-CH2CH218F and BNL-26d-CH2CH218F. These nuclear medicine with imaging agents can be used as a tracer in vivo binding to over-expression HDAC and produce a HDAC nuclear medicine imaging effect to serve for clinical diagnosis. The second part of the method is to provide a slightly adjusted a structural framework of BNL-26 and use pyridine to substitute the benzene ring of the BNL-26 structure, and then synthesize with other substituent to produce a series of additional 30 more HDAC inhibitors, named from Iner-1 to Iner-30 compounds.

Abstract: A jitter-based transmission control method is disclosed. In the jitter-based transmission control method, several packets are sent applying a current congestion window size by at least one sender device through a network switch device. An immediate jitter ratio of the network switch device is calculated by the sender device. An average jitter ratio of the network switch device is updated by the sender device according to the immediate jitter ratio and the current congestion window size. The current congestion window size is reduced when the immediate jitter ratio or the updated average jitter ratio is positive and larger than a queued threshold over the current congestion window size, such that the packets are sent applying the reduced current congestion window size.

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract: A jitter-based transmission control method is disclosed. In the jitter-based transmission control method, several packets are sent applying a current congestion window size by at least one sender device through a network switch device. An immediate jitter ratio of the network switch device is calculated by the sender device. An average jitter ratio of the network switch device is updated by the sender device according to the immediate jitter ratio and the current congestion window size. The current congestion window size is reduced when the immediate jitter ratio or the updated average jitter ratio is positive and larger than a queued threshold over the current congestion window size, such that the packets are sent applying the reduced current congestion window size.

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract: A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.

Abstract: The present invention relates to a method for producing a mammal reconstruction cell, a method for producing a nuclear transferred (NT) embryo capable of developing into a non-human mammal, a method for producing a non-human mammal fetus, a method for producing a non-human mammal and the products prepared by the foregoing methods.

Abstract: A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.

Abstract: An encode device, comprises a light source, an encode wheel and a light detector. A hollow dent is formed on the center part of the incident plane of the encode wheel. The inner circumference of the dent is provided with a ring-shaped lens such that the light impinging on the inner circumference of the dent is focused by the ring-shaped lens. The rim of the encode wheel is provided with a plurality of cylindrical lenses which are perpendicular to the ring-shaped lens such that the light leaving the encode wheel can be further focused. Therefore, the working beam projected toward the chip of the light detector has less interference.