Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the bather layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: The present disclosure is directed to an interconnect structure. The metal interconnect structure has a metal body disposed over a semiconductor substrate and a projection extending from the metal body. A barrier layer continuously extends over the projection from a first sidewall of metal body to an opposing second sidewall of the metal body. A layer of dielectric material is disposed over the semiconductor substrate at a position abutting the metal body and the projection.

Abstract: A method includes depositing a first polymer layer over a first dielectric layer, forming a first opening and a second opening using an etching process, wherein the first opening and the second opening are partially through the first polymer layer, filling the first opening and the second opening with a conductive material to form a first metal line and a second metal line, applying a selective thermal curing process to the first polymer layer until portions of the first polymer layer surrounding the first metal line and the second metal line are cured, removing uncured portions of the first polymer layer through a cleaning process and depositing a second dielectric layer to form an air gap between the first metal line and the second metal line.

Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.

Abstract: A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions of the first conductive layer outside the plurality of first openings, the patterned mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings. A second conductive layer is filled in the plurality of second openings. The patterned mask layer is removed to leave behind the conductive layer structures on the substrate. The substrate is heated to form a self-forming barrier layer on the top and sidewalls of the conductive layer structures.

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.

Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract: Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.

Abstract: A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer.

Abstract: A device includes a first conductive line in a first metallization layer over a dielectric layer, wherein the first conductive line is wrapped by a first polymer layer on three sides and the first conductive line and the dielectric layer are separated by a bottom portion of the first polymer layer, a second conductive line over the dielectric layer, wherein the second conductive line is wrapped by a second polymer layer on three sides and the second conductive line and the dielectric layer are separated by a bottom portion of the second polymer layer and an air gap between the first conductive line and the second conductive line.

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.