Patents by Inventor Hsiang Liu

Hsiang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220301919
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Yu-Hsiang HU, Chung-Shi LIU, Hung-Jui KUO, Ming-Da CHENG
  • Patent number: 11450579
    Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11448891
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yu Chen, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Yen-Chiang Liu, Jiun-Jie Chiou, Li-Yang Tu, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Hsi-Cheng Hsu
  • Patent number: 11448897
    Abstract: A three-dimensional imaging system and method are provided. The three-dimensional imaging system includes a suspension force field generator, a projection module, and a controller. The suspension force field generator generates a suspension force field to suspend a plurality of scattering particles used for scattering incident light and distribute the scattering particles on a projection plane. The projection module projects an image on the projection plane. The controller is coupled to the suspension force field generator and the projection module, controls the suspension force field generator to change the suspension force field so that the projection plane where the scattering particles are distributed moves in a display space, extracts a slice plane image that matches a position of the projection plane from multiple slice plane images sliced from a three-dimensional stereoscopic image, and controls the projection module to project the extracted slice plane image to the projection plane.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 20, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Ju Lee, Shin-Hong Kuo, Yu-Hsiang Liu, Kuan-Ting Chen
  • Patent number: 11450769
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11446851
    Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
  • Publication number: 20220291161
    Abstract: A system and a method for measuring a void fraction of an inside of a heat conduction member are provided. The system is used to measure the heat conduction member and includes: a heating device configured as a heat source to heat an evaporation end of the heat conduction member; a cooling device configured for cooling a condensation end of the heat conduction member; at least one pair of electrode pads respectively attached to two opposite surfaces of the heat conduction member; and an LCR meter electrically connected to the at least one pair of the electrode pads for measuring impedances of the heat conduction member. Each of the impedances is converted into the void fraction that corresponds to a measured position of the heat conduction member.
    Type: Application
    Filed: November 18, 2021
    Publication date: September 15, 2022
    Inventors: CHEN-LI SUN, YU-HSIANG LIU, YU-JEN LIEN
  • Publication number: 20220291366
    Abstract: An underwater ultrasonic device is disclosed. The underwater ultrasonic device comprises a body and an ultrasonic transducer. The ultrasonic transducer has a curved interface having a first side and an adjacent second side for transmitting and receiving a plurality of ultrasonic signals, and the first side has a first curve and the second side has a second curve, wherein the first curve and the second curve has different curvatures. Therefore, the underwater ultrasonic device can achieve the purpose of underwater wide-angle measurement with increased sensitivity and transmission capability.
    Type: Application
    Filed: January 19, 2022
    Publication date: September 15, 2022
    Applicant: Qisda Corporation
    Inventors: Fu-Sheng JIANG, Yi-Hsiang CHAN, Hsin-Chih LIU
  • Publication number: 20220291963
    Abstract: An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 15, 2022
    Inventors: Fu-Chun CHANG, Ta-Wei LIU, Cheng-Xin XUE, Sheng-Po HUANG, Yen-Hsiang HUANG, Meng-Fan CHANG
  • Publication number: 20220285168
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
  • Patent number: 11437161
    Abstract: An apparatus includes an extreme ultraviolet light source vessel having an intermediate focus, a scanner having a light source aperture, and a deflection module arranged between the intermediate focus and the light source aperture. The deflection module includes a first electrode plate and a second electrode plate, configured to create an electric field therebetween. Tin particles moving from the intermediate focus to the light source aperture passes through the deflection module, and are deflected by the electric field therein.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Lin Chang, Chieh Hsieh, Shang-Chieh Chien, Han-Lung Chang, Heng-Hsin Liu, Li-Jui Chen, Chin-Hsiang Lin
  • Patent number: 11435817
    Abstract: A multi-power management system and an operation method for the multi-power management system are provided. The multi-power management system includes multiple adapters and a power supply circuit. The adapters respectively provide multiple powers. The power supply circuit receives multiple input power values of the adapters, and calculates multiple input power value contribution ratios of the adapters according to the input power values. The power supply circuit further provides a control signal according to a sum of the output current values of multiple output current values of the powers and the input power value contribution ratios. The adapters adjust the output current values and multiple output voltage values respectively in response to the control signal.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 6, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chin-Hsiang Lin, Chien-Lee Liu, Tzu-Chiang Mi, Yi-Hsun Lin
  • Patent number: 11430671
    Abstract: A wafer cleaning module and a method for cleaning a wafer with the wafer cleaning module are disclosed. For example, the wafer cleaning module includes a wafer chuck to hold a wafer, an ozone source to provide ozone gas towards the wafer, and an ultraviolet (UV) lamp module to provide UV light. The UV lamp module includes a UV light source and a rotatable reflector around the UV light source. The rotatable reflector is movable to adjust an amount of UV light directed towards a surface of the wafer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yang Lin, Chung-Hsuan Liu, Ku-Hsiang Sung, Kuan-Wen Lin, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 11430108
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 11431440
    Abstract: An iterative detection and decoding (IDD) circuit is provided. The iterative detection and decoding (IDD) circuit is configured to perform M outer iterations on a received signal, and Ni inner iterations are performed during the ith outer iteration of the M outer iterations, where M is an integer greater than 1, i is an integer less than or equal to M, and N1 to NM are integers and include at least two different values.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 30, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Hsiang Yang, Yao-Pin Wang, Chi-Chih Wen, Der-Zheng Liu, Chung-Jung Huang
  • Patent number: 11429027
    Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Chin-Hsiang Lin
  • Publication number: 20220266293
    Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.
    Type: Application
    Filed: October 26, 2021
    Publication date: August 25, 2022
    Inventors: CHIA-SHENG HUANG, CHI-LING LIN, CHIA-CHENG WU, CHING-HSIANG LIU
  • Patent number: 11422819
    Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kai-Chi Huang, Chi-Lin Liu, Wei-Hsiang Ma, Shang-Chih Hsieh
  • Patent number: 11422357
    Abstract: An optical system is provided and includes a fixed assembly, a movable element and a driving module. The fixed assembly has a main axis. The movable element is movable relative to the fixed assembly, and the movable element is connected to a first optical element. The driving module is configured to drive the movable element to move relative to the fixed assembly.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Publication number: 20220262301
    Abstract: A display device with sensing element includes a substrate having a disposing surface, a plurality of display elements, at least one sensing element, and at least one lighting adjustment element. The display elements are disposed above the disposing surface to present an image. The at least one sensing element disposed above the disposing surface to sense a light brightness projected toward either side of the substrate. The at least one light adjustment element is in signal transmittable connection with the display elements and the at least one sensing element. The at least one light adjustment element adjusts a plurality of control signals inputted into the display elements to determine a contrast of the image.
    Type: Application
    Filed: November 18, 2021
    Publication date: August 18, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Yu KUO, Wei-Chung CHEN, Yi-Hsiang HUANG, Yu- Hsiang LIU