Patents by Inventor Hsiao-Chin Tuan
Hsiao-Chin Tuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140284706Abstract: A semiconductor device includes a buried layer having a first dopant type in a substrate. The semiconductor device includes a first layer having the first dopant type over the buried layer. The semiconductor device includes at least one first well of a second dopant type disposed in the first layer. The semiconductor device includes an implantation region of the second dopant type in a sidewall of the first layer, wherein the implantation region is below the at least one first well. The semiconductor device includes a first source region disposed in the at least one first well; and at least one gate disposed on top of the first well and the first layer. The semiconductor device includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.Type: ApplicationFiled: June 11, 2014Publication date: September 25, 2014Inventors: Chih-Chang CHENG, Ruey-Hsin LIU, Chih-Wen YAO, Hsiao Chin TUAN
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Publication number: 20140273376Abstract: A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.Type: ApplicationFiled: February 20, 2014Publication date: September 18, 2014Inventors: Alexander Kalnitsky, Kong-Beng Thei, Chien-Chih Chou, Chen-Liang Chu, Hsiao-Chin Tuan
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Patent number: 8779505Abstract: A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer.Type: GrantFiled: May 2, 2013Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Hsiao Chin Tuan
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Publication number: 20140167127Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 8704312Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.Type: GrantFiled: January 5, 2010Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Chia-Chin Shen, Eric Huang, Fu Chin Yang, Chun Lin Tsai, Hsiao-Chin Tuan
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Patent number: 8664718Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate.Type: GrantFiled: January 11, 2012Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Hsiao-Chin Tuan
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Patent number: 8633086Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.Type: GrantFiled: December 31, 2009Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Liang-Kai Han, Uway Tseng, Yuan-Chih Hsieh, Hung-Hua Lin
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Publication number: 20130277736Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) includes an epitaxial layer over a substrate a first trench in the epitaxial layer and a second trench in the epitaxial layer. A depth of the first trench is different from a depth of the second trench. The trench MOSFET further includes a source region surrounding the self-aligned source contact, wherein the source region is convex-shaped. The trench MOSFET further includes a self-aligned source contact between the first trench and the second trench; wherein the self-aligned source contact is connected to the source region.Type: ApplicationFiled: June 19, 2013Publication date: October 24, 2013Inventors: Alex KALNITSKY, Hsiao-Chin TUAN, Kuo-Ming WU, Wei Tsung HUANG
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Patent number: 8507988Abstract: A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.Type: GrantFiled: June 2, 2010Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Yao, Robert S. J. Pan, Ruey-Hsin Liu, Hsueh-Liang Chou, Puo-Yu Chiang, Chi-Chih Chen, Hsiao Chin Tuan
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Patent number: 8497551Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.Type: GrantFiled: June 2, 2010Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Kuo-Ming Wu, Wei Tsung Huang
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Publication number: 20130146893Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.Type: ApplicationFiled: February 6, 2013Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng THEI, Jiun-Lei Jerry YU, Chun Lin TSAI, Hsiao-Chin TUAN, Alex KALNITSKY
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Patent number: 8461647Abstract: A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.Type: GrantFiled: March 10, 2010Date of Patent: June 11, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Liang Chou, Ruey-Hsin Liu, Chih-Wen Yao, Hsiao-Chin Tuan
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Publication number: 20130140667Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alex KALNITSKY, Chih-Wen YAO, Jun CAI, Ruey-Hsin LIU, Hsiao-Chin TUAN
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Publication number: 20130134512Abstract: A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region.Type: ApplicationFiled: January 11, 2012Publication date: May 30, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Hsiao-Chin Tuan
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Patent number: 8445955Abstract: A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.Type: GrantFiled: February 3, 2010Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Hsiao Chin Tuan
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Patent number: 8390024Abstract: An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.Type: GrantFiled: April 9, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liping Ren, Hsiao-Chin Tuan, Dah-Chuen Ho
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Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics
Patent number: 8389348Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.Type: GrantFiled: September 14, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Jiun-Lei Jerry Yu, Chun Lin Tsai, Hsiao-Chin Tuan, Alex Kalnitsky -
MECHANISM OF FORMING SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS
Publication number: 20120061681Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.Type: ApplicationFiled: September 14, 2010Publication date: March 15, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng THEI, Jiun-Lei Jerry YU, Chun Lin TSAI, Hsiao-Chin TUAN, Alex KALNITSKY -
Publication number: 20110298045Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Inventors: Alex KALNITSKY, Hsiao-Chin TUAN, Kuo-Ming WU, Wei Tsung HUANG
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Publication number: 20110260245Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. In an embodiment, an apparatus includes a substrate having a first surface and a second surface, the second surface being opposite the first surface; a first device and a second device overlying the substrate; and an isolation structure that extends through the substrate from the first surface to the second surface and between the first device and the second device.Type: ApplicationFiled: April 23, 2010Publication date: October 27, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ruey-Hsin LIU, Puo-Yu CHIANG, Chih-Wen YAO, Yu-Chang JONG, Hsiao-Chin TUAN