Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and a surface portion formed on the blocking layer.

Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.

Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

Abstract: A resistive random access memory (RRAM) cell includes a substrate, a transistor having a gate on the substrate and a source/drain region in the substrate, a first inter-layer dielectric layer covering the transistor, a contact plug disposed in the first inter-layer dielectric layer and landing on the source/drain region, a resistive material layer conformally covering a protruding upper end portion of the contact plug, and a top electrode on the resistive material layer.

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.

Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.