Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract: A plasma processing device has a housing, a metal plate, an inner ring, and an outer ring. A vacuum chamber is formed in the housing. An air vent is installed on an upper end of the vacuum chamber for venting gaseous reactants into the vacuum chamber when performing a plasma process. The metal plate has a channel for venting gaseous matter and at least a vertical vent hole for guiding the gaseous reactants into the vacuum chamber. The inner ring and the outer ring are positioned between the housing and the metal plate, and the inner ring is surrounded by the outer ring. An air chamber formed between the inner ring and the outer ring connects with the channel of the metal plate.

Abstract: The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The dielectric layer has a via opening exposing the conductive structure. The via opening is filled with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer. The GFP layer is etched back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening. A surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer is then carried out, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.

Abstract: A plasma arcing sensor is used to increase the frequency of plasma arcing by way of neutralization of positive charges and negative charges. When the plasma arcing can be predicted, the process parameters to prevent from the plasma arcing can be carried out. The plasma arcing sensor comprises a top conductive layer formed over a substrate. A conductive layer is disposed between the top conductive layer and the wafer where the conductive layer and the top conductive layer are electrically isolated with dielectrics.

Abstract: A method for removing residual color photoresist material from a substrate after photoresist development. The method washes the substrate with a high-pressure jet of de-ionized water that contains an activated interface agent. A second method of removing the residual photoresist material bombards the substrate with oxygen plasma for a brief period so that the residual photoresist material is polarized and then rinses the substrate with de-ionized water.

Abstract: A method for removing residual color photoresist material from a substrate after photoresist development. The method washes the substrate with a high-pressure jet of de-ionized water that contains an activated interface agent. A second method of removing the residual photoresist material bombards the substrate with oxygen plasma for a brief period so that the residual photoresist material is polarized and then rinses the substrate with de-ionized water.

Abstract: A method for forming an opening is provided. The method contains forming a dielectric layer on the substrate. The dielectric layer is patterned to form a first-stage opening. A carbonic-polymer (C-polymer) concentration controlling treatment is performed to obtain a proper C-polymer concentration, which can be raised, reduced, or even down to a zero concentration. After the proper C-polymer concentration is obtained, a next-stage opening is formed by another step of etching. The C-polymer concentration controlling treatment and the etching process with a new condition for each step can be repeated until a desired opening is formed.

Abstract: A method of improving an etch back process. A substrate having a metal layer formed thereon is provided. A main etching is performed over the metal layer to form an interconnect. A first over etching is performed over a metal residue left after the main etching. A gas flush and second over etch are performed.

Abstract: A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.

Abstract: A method for forming an opening in a semiconductor device is provided. A silicon-oxy-nitride layer is formed on a dielectric layer and then a photoresist layer with a first opening is formed on the silicon-oxy-nitride layer. A polymer film is formed on sidewalls of the first opening. A second opening narrower than the first opening is formed in the dielectric layer with the photoresist layer and the polymer film.

Abstract: A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

Abstract: A dual damascene processing method comprising the steps depositing sequentially a first oxide layer, a SRO layer and a second oxide layer over a substrate. Then, photolithographic and etching operations are conducted to form a via that links up with a desired wire-connecting region above the substrate. Next, another photolithographic and etching operations are conducted to form interconnect trench lines followed by the deposition of metal into the via and trench. Finally, the surface is polished with a chemical-mechanical polishing operation to remove the unwanted metal on the surface. The invention is capable of controlling the depth of trench and obtaining a smoother trench bottom for the metal lines. Furthermore, the separation of via and trench etching steps makes the control of the final etch profile much easier, thereby able to get an optimal result.

Abstract: A etchant recipe including a mixed gas of one of a CH.sub.x F.sub.y group and CO gas is used to etch a silicon nitride layer by plasma etching so as to form a thin polymer layer to protect a silicon layer under the silicon nitride layer from over-etching. Then a soft etching is performed to remove the thin polymer. The etchant recipe is, for example, used in forming a contact opening on a gate of a MOS transistor, on which a silicon nitride layer is formed.