Patents by Inventor Hsiao-Tzu Lu
Hsiao-Tzu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9852251Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.Type: GrantFiled: March 10, 2014Date of Patent: December 26, 2017Assignee: SYNOPSYS, INC.Inventors: Hsiao-Tzu Lu, Duncan Robert McDonald, Chih-Wei Yuan, Wen-Lung Kang
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Patent number: 8969922Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.Type: GrantFiled: February 8, 2012Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Mu-Chi Chiang, Yao-Kwang Wu, Bi-Fen Wu, Huan-Just Lin, Hsiao-Tzu Lu, Hui-Chi Huang
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Patent number: 8893069Abstract: A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.Type: GrantFiled: October 6, 2012Date of Patent: November 18, 2014Assignees: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Yu-Chi Su, Ming-I Lai, Hsiao-Tzu Lu
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Publication number: 20140304671Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.Type: ApplicationFiled: March 10, 2014Publication date: October 9, 2014Applicant: Synopsys, Inc.Inventors: Hsiao-Tzu LU, Duncan Robert McDONALD, Chih-Wei YUAN, Wen-Lung KANG
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Patent number: 8815496Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: February 22, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Kuei Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
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Patent number: 8707226Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.Type: GrantFiled: June 6, 2011Date of Patent: April 22, 2014Assignee: Synopsys, Inc.Inventors: Hsiao-Tzu Lu, Duncan Robert McDonald, Chih-Wei Yuan, Wen-Lung Kang
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Publication number: 20130200461Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chu Liu, Kuei Shun Chen, Mu-Chi Chiang, Yao-Kwang Wu, Bi-Fen Wu, Huan-Just Lin, Hsiao-Tzu Lu, Hui-Chi Huang
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Publication number: 20130091481Abstract: A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively.Type: ApplicationFiled: October 6, 2012Publication date: April 11, 2013Inventors: Yu-Chi Su, Ming-I Lai, Hsiao-Tzu Lu
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Patent number: 8394576Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: January 10, 2012Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Kuei Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
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Publication number: 20120293782Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.Type: ApplicationFiled: August 1, 2012Publication date: November 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Hung Chang Hsieh, Kuei Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh, Shau-Lin Shue
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Patent number: 8236579Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.Type: GrantFiled: March 14, 2007Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Hung Chang Hsieh, Kuei Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh, Shau-Lin Shue
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Publication number: 20120114872Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: ApplicationFiled: January 10, 2012Publication date: May 10, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
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Patent number: 8124323Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: September 25, 2007Date of Patent: February 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
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Patent number: 8119992Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.Type: GrantFiled: August 7, 2009Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Publication number: 20110307854Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.Type: ApplicationFiled: June 6, 2011Publication date: December 15, 2011Inventors: HSIAO-TZU LU, Duncan Robert McDonald, Chih-Wei Yuan, Wen-Lung Kang
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Patent number: 7723014Abstract: A method for photolithography in semiconductor manufacturing includes providing a substrate for a wafer and providing a mask for exposing the wafer. The wafer is exposed by utilizing a combination of high angle illumination and focus drift exposure methods.Type: GrantFiled: October 26, 2005Date of Patent: May 25, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Tsai-Cheng Gau, Chun-Kung Chen, Hsiao-Tzu Lu, Fu-Jye Liang
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Publication number: 20090294685Abstract: Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Patent number: 7601466Abstract: A method for photolithography in semiconductor manufacturing includes providing a mask with first and second focus planes for a wafer. The wafer includes corresponding first and second wafer regions. The first wafer region receives a first image during a first exposure utilizing the first focus plane. The second wafer region receives a second image during a second exposure utilizing the second focus plane.Type: GrantFiled: February 9, 2005Date of Patent: October 13, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Sung Yen, Kuei Shun Chen, Chia-Sui Hsu, Yuh-Sen Chang, Hsiao-Tzu Lu
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Patent number: 7582538Abstract: A method for semiconductor manufacturing includes forming an overlay target having a pattern formed by a first mask layer and an adjacent layer. The overlay target is exposed to radiation. As a result, reflective beams can be detected from the pattern and the adjacent layer and the location of the pattern can be identified based on the reflective beams.Type: GrantFiled: April 6, 2005Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Chin-Hsiang Lin, Hua-Shu Wu, Chia-Hsiang Lin, Kuei Shun Chen
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Publication number: 20090081591Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu