Patents by Inventor Hsiao-Ying Yang
Hsiao-Ying Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973021Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.Type: GrantFiled: September 17, 2021Date of Patent: April 30, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Kai-Chun Chen, Shih-Ming Tseng, Hsing-Chao Liu, Hsiao-Ying Yang
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Publication number: 20240136447Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first deep well region, at least two second well regions, at least one isolation structure and an implantation region. The first deep well region is disposed in the semiconductor substrate, wherein the first deep well region has a first conductivity type. The second well regions are disposed on the first deep well region, wherein the second well regions have a second conductivity type. The isolation structure covers a portion of the first deep well region and surrounds at least a portion of the second well regions. The implantation region is located under a top surface of the semiconductor substrate, wherein the implantation region has a discontinuous portion, and the discontinuous portion partially overlaps the first deep well region.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Chung-Ren LAO, Hsiao-Ying YANG, Hsing-Chao LIU, Ching-Chung CHEN
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Patent number: 11742389Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.Type: GrantFiled: May 18, 2021Date of Patent: August 29, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hung-Chih Tan, Hsing-Chao Liu, Chih-Cherng Liao, Hsiao-Ying Yang, Kai-Chuan Kan, Jing-Da Li
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Publication number: 20230238262Abstract: A semiconductor manufacturing process prediction method and a semiconductor manufacturing process prediction device are provided. The semiconductor manufacturing process prediction method includes the following steps. A plurality of process data are obtained. According to the process data, a machine learning model is used to execute prediction and obtain a prediction confidence and a prediction yield. Whether the prediction confidence is lower than a predetermined level is determined. If the prediction confidence is lower than the predetermined level, the machine learning model is modified. According to the process data, the prediction yield is adjusted.Type: ApplicationFiled: March 15, 2022Publication date: July 27, 2023Inventors: Hsiao-Ying YANG, Ching-Pei LIN, Chung-Yi CHIU, Ming-Wei CHEN, Te-Hsuan CHEN, Chia-Wei CHEN, Wen-Shan HUANG
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Publication number: 20230236553Abstract: A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.Type: ApplicationFiled: March 15, 2022Publication date: July 27, 2023Inventors: Chia-Wei CHEN, Ching-Pei LIN, Chung-Yi CHIU, Te-Hsuan CHEN, Ming-Wei CHEN, Hsiao-Ying YANG
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Publication number: 20230105036Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.Type: ApplicationFiled: September 17, 2021Publication date: April 6, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Kai-Chun CHEN, Shih-Ming TSENG, Hsing-Chao LIU, Hsiao-Ying YANG
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Publication number: 20220376052Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Hung-Chih TAN, Hsing-Chao LIU, Chih-Cherng LIAO, Hsiao-Ying YANG, Kai-Chuan KAN, Jing-Da LI
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Patent number: 11393921Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.Type: GrantFiled: August 26, 2020Date of Patent: July 19, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Hung-Chih Tan, Hsing-Chao Liu, Hsiao-Ying Yang, Chih-Cherng Liao
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Publication number: 20220216308Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
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Patent number: 11374096Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.Type: GrantFiled: January 4, 2021Date of Patent: June 28, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
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Publication number: 20220069122Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Inventors: Hung-Chih Tan, Hsing-Chao Liu, Hsiao-Ying Yang, Chih-Cherng Liao
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Patent number: 11164979Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.Type: GrantFiled: August 6, 2020Date of Patent: November 2, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Gong-Kai Lin, Yeh-Ning Jou, Chien-Hsien Song, Hsiao-Ying Yang, Chien-Chi Hsu, Fu-Chun Tseng
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Patent number: 10276493Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.Type: GrantFiled: August 1, 2017Date of Patent: April 30, 2019Assignee: VANGUARD ENTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wei-Lun Hsia, Chun-Hsien Lin, Hsiao-Ying Yang
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Publication number: 20190043801Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.Type: ApplicationFiled: August 1, 2017Publication date: February 7, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Wei-Lun HSIA, Chun-Hsien LIN, Hsiao-Ying YANG
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Patent number: 9219012Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: November 11, 2011Date of Patent: December 22, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Publication number: 20120056295Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: CHIH-PING LIN, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 8080455Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: July 22, 2008Date of Patent: December 20, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 8067283Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.Type: GrantFiled: November 13, 2009Date of Patent: November 29, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Shih-Ming Chen, Hsiao-Ying Yang, Wen-Hsien Liu, Po-Sheng Hu
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Patent number: 8063439Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: GrantFiled: November 23, 2010Date of Patent: November 22, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
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Publication number: 20110117709Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ping LIN, Shih-Ming CHEN, Hsiao-Ying YANG, Wen-Hsien LIU, Po-Sheng HU