Patents by Inventor Hsien-Chang Chang

Hsien-Chang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060270071
    Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
    Type: Application
    Filed: April 20, 2006
    Publication date: November 30, 2006
    Inventors: Hsien-Chang Chang, Chia-Hsin Hou, Tsu-Yu Chu, Ko-Ting Chen
  • Publication number: 20050087444
    Abstract: A method for manufacturing a microfluidic chip with electroosmotic flow (EOF) controlled by inducing a perpendicularly electric field through a self-assembled monolayer (SAM) is disclosed. The method is primarily to combine a top plate and a bottom plate; wherein the bottom plate has a gate electrode on an upper surface thereof and has the SAM formed on said gate electrode. The top plate has an elongate micro channel groove which is narrower than that of the gate electrode, recessed in a lower portion thereof and filled with a buffer solution. Accordingly, the flowing direction and the flowing velocity of said EOF are controlled by supplying high voltage to two ends of said micro channel groove to produce an electric field for driving EOF and supplying an inducing voltage to the gate electrode. The SAM of the present invention can be easily formed and thin enough to lower the inducing voltage required for controlling the zeta potential and have a smaller chip size.
    Type: Application
    Filed: October 23, 2003
    Publication date: April 28, 2005
    Inventors: Hsien-Chang Chang, Ching-Chou Wu, Ren-Guen Wu
  • Patent number: 6689572
    Abstract: A method for detecting Escherichia coli in a sample by providing a sample suspected of containing Escherichia coli; contacting the sample with beads coated with a mixture of antibodies or anti-serum specific to one or more surface antigens of Escherichia coli, each of the one or more surface antigens having a molecular weight of 21±2 KDa, 26±2 KDa, 31±2 KDa, 36±2 KDa, 38±2 KDa, 67±2 KDa, or 77.8±2 KDa; and observing agglutination of the beads, where the presence of the agglutination indicates the presence of Escherichia coli in the sample.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: February 10, 2004
    Assignee: Executive Yuan, Council of Agriculture
    Inventors: Ya Hei Huang, Hsien-Chang Chang, Tsung Chain Chang
  • Patent number: 5283181
    Abstract: A conjugated enzyme electrode comprising diaphorase and an amino-acid dehydrogenase immobilized on a conductive support by a polyfunctional aldehyde is disclosed, by which amino acids can be rapidly determined with high sensitivity.
    Type: Grant
    Filed: March 20, 1991
    Date of Patent: February 1, 1994
    Assignee: Unitika, Ltd.
    Inventors: Isamu Uchida, Tomokazu Matsue, Hsien-Chang Chang, Akinori Ueno, Hiroshi Yamada