Patents by Inventor Hsien-Chang Wu
Hsien-Chang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006233Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Kang FU, Hsien-Chang WU, Ming-Han LEE, Shau-Lin SHUE
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Patent number: 11127680Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: GrantFiled: June 23, 2017Date of Patent: September 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue
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Patent number: 10930552Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: GrantFiled: October 21, 2019Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Publication number: 20200051857Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 10453746Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: GrantFiled: April 16, 2018Date of Patent: October 22, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 10160174Abstract: Disclosed are a method of manufacturing sport protective equipment and sport protective equipment manufactured by the method. A thin casing is manufactured by a thin sheet material in a vacuum forming process; protrusions are formed apart from one another on a surface of the thin casing; a containing space is formed on an inner side of each protrusion for filling a filler; and a substrate is provided to seal the bottom of the thin casing, so that the filler in each of the containing spaces will not fall out, so as to improve the manufacturing efficiency and the product quality. The sport protective equipment manufactured by this method does not require any sewing manufacture or increase thickness, so that the flexibility of wearing and using is improved, and the thin casing and the filler are provided for absorbing shocks to improve the protective effect.Type: GrantFiled: September 30, 2015Date of Patent: December 25, 2018Inventors: Hsien-Chang Wu, Hung-Sung Hsu
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Publication number: 20180233406Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 9947583Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: GrantFiled: February 13, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 9935006Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: GrantFiled: March 2, 2017Date of Patent: April 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Chang Wu, Li-Lin Su
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Publication number: 20170287842Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: ApplicationFiled: June 23, 2017Publication date: October 5, 2017Inventors: Shih-Kang FU, Hsien-Chang WU, Li-Lin SU, Ming-Han LEE, Shau-Lin SHUE
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Patent number: 9721894Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: GrantFiled: November 28, 2016Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20170178957Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Inventors: Hsien-Chang Wu, Li-Lin Su
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Publication number: 20170170066Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: ApplicationFiled: February 13, 2017Publication date: June 15, 2017Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 9627256Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.Type: GrantFiled: February 27, 2013Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Bo-Jiun Lin, Hsien-Chang Wu
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Publication number: 20170087786Abstract: Disclosed are a method of manufacturing sport protective equipment and sport protective equipment manufactured by the method. A thin casing is manufactured by a thin sheet material in a vacuum forming process; protrusions are formed apart from one another on a surface of the thin casing; a containing space is formed on an inner side of each protrusion for filling a filler; and a substrate is provided to seal the bottom of the thin casing, so that the filler in each of the containing spaces will not fall out, so as to improve the manufacturing efficiency and the product quality. The sport protective equipment manufactured by this method does not require any sewing manufacture or increase thickness, so that the flexibility of wearing and using is improved, and the thin casing and the filler are provided for absorbing shocks to improve the protective effect.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Hsien-Chang Wu, Hung-Sung Hsu
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Publication number: 20170092591Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: ApplicationFiled: November 28, 2016Publication date: March 30, 2017Inventors: Shih-Kang FU, Hsien-Chang WU, Li-Lin SU, Ming-Han LEE, Shau-Lin SHUE
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Patent number: 9589897Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: GrantFiled: August 18, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Chang Wu, Li-Lin Su
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Publication number: 20170053876Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: ApplicationFiled: August 18, 2015Publication date: February 23, 2017Inventors: Hsien-Chang Wu, Li-Lin Su
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Patent number: 9570347Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.Type: GrantFiled: June 8, 2015Date of Patent: February 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu, Hsiang-Huan Lee
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Patent number: 9530737Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: GrantFiled: September 28, 2015Date of Patent: December 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue