Patents by Inventor Hsien-Cheng Wang
Hsien-Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Patent number: 11682579Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: GrantFiled: May 27, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Publication number: 20220293461Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Patent number: 11348830Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: GrantFiled: December 7, 2020Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Patent number: 11244832Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.Type: GrantFiled: July 27, 2020Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
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Patent number: 11121128Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.Type: GrantFiled: May 22, 2020Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chang Wen, Chun-Kuang Chen, Hsien-Cheng Wang
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Publication number: 20210090943Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Publication number: 20200388498Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.Type: ApplicationFiled: July 27, 2020Publication date: December 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
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Patent number: 10861740Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: GrantFiled: May 6, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Patent number: 10790197Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: December 16, 2019Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Publication number: 20200286887Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Inventors: Ming-Chang Wen, Chun-Kuang Chen, Hsien-Cheng Wang
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Patent number: 10727068Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.Type: GrantFiled: October 8, 2019Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Hsiao-Chiu Hsu
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Patent number: 10665585Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.Type: GrantFiled: April 6, 2015Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chang Wen, Chun-Kuang Chen, Hsien-Cheng Wang
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Publication number: 20200118884Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: I-Wen WU, Hsien-Cheng WANG, Mei-Yun WANG, Shih-Wen LIU, Chao-Hsun WANG, Yun LEE
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Publication number: 20200051821Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.Type: ApplicationFiled: October 8, 2019Publication date: February 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
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Patent number: 10510614Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: GrantFiled: April 29, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10468257Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.Type: GrantFiled: August 18, 2016Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
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Publication number: 20190259657Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
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Publication number: 20190252265Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
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Patent number: 10283403Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.Type: GrantFiled: October 2, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang