Patents by Inventor Hsien-Ching Lo

Hsien-Ching Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714577
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo
  • Patent number: 10700173
    Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang, Ruilong Xie, Haiting Wang, Hui Zhan, Yong Jun Shi
  • Patent number: 10636894
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Publication number: 20200105584
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Wei HONG, Hui ZANG, Hsien-Ching LO, Zhenyu HU, Liu JIANG
  • Publication number: 20200105886
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 2, 2020
    Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo
  • Publication number: 20200066883
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • Patent number: 10559656
    Abstract: Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emilie M. S. Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang, Hsien-Ching Lo, Zhenyu Hu
  • Publication number: 20200043779
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Wei Hong, Liu Jiang, Yongjun Shi, Yi Qi, Hsien-Ching Lo, Hui Zang
  • Patent number: 10553707
    Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo, Zhaoying Hu
  • Patent number: 10546775
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Liu Jiang, Yongjun Shi, Yi Qi, Hsien-Ching Lo, Hui Zang
  • Publication number: 20200027821
    Abstract: A chip on film package including a chip and a flexible film. The chip includes bumps disposed on the chip and is mounted on the flexible film. The flexible film includes first vias, second vias, upper leads and lower leads. The first vias and the second vias penetrate the flexible film and are arranged on two opposite sides of a reference line respectively. A distance between one of the first vias and one of the second vias, which are closer to a first side of the chip, is longer than that between another one of the first vias and another one of the second, which are further from the first side. The upper leads are disposed on the upper surface connected between the vias and the bumps. The lower leads are disposed on the lower surface and connected to the vias.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 23, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Hsien-Wen Lo, Wen-Ching Huang
  • Publication number: 20200020770
    Abstract: Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Yi Qi, Hsien-Ching Lo, Xusheng Wu, Hui Zang, Zhenyu Hu, George R. Mulfinger
  • Publication number: 20190341448
    Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: Emilie M.S. Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang, Hsien-Ching Lo, Zhenyu Hu
  • Patent number: 10461155
    Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
  • Publication number: 20190312117
    Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang, Ruilong Xie, Haiting Wang, Hui Zhan, Yong Jun Shi
  • Patent number: 10431665
    Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
  • Publication number: 20190280105
    Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi, Wei Hong, Yongjun Shi, Jae Gon Lee, Chun Yu Wong
  • Patent number: 10410929
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie
  • Patent number: 10388652
    Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann, Chanro Park, Daniel Chanemougame, Min Gyu Sung, Hsien-Ching Lo, Haiting Wang
  • Patent number: 10355104
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, Jr., Shesh Mani Pandey