Patents by Inventor Hsien-Ching Lo
Hsien-Ching Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10068810Abstract: A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins may be formed by etching an active epitaxial layer that is disposed over the substrate. An intervening sacrificial epitaxial layer may be used to template growth of the active epitaxial layer, and is then removed and backfilled with an isolation dielectric layer. The isolation dielectric layer may be disposed between bottom surfaces of the fins and the substrate, and may be deposited, for example, following the etching process used to define the fins. Within different regions of the substrate, dielectrically isolated fins of different heights may have substantially co-planar top surfaces.Type: GrantFiled: September 7, 2017Date of Patent: September 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Yi Qi, Jianwei Peng, Hsien-Ching Lo, Sipeng Gu
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Patent number: 10050125Abstract: Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.Type: GrantFiled: August 14, 2017Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Yi Qi, Hui Zang, Xusheng Wu, Hsien-Ching Lo
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Publication number: 20180190792Abstract: The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially U-shaped and self-aligned with the first spacer. The semiconductor structure including: a fin; a gate stack substantially surrounding the fin; a first pair of spacers over the fin and laterally adjacent to the gate stack; and a pair of substantially U-shaped cavities within the fin and on opposing sides of the gate stack, the pair of substantially U-shaped cavities being self-aligned with the first pair of spacers, wherein the pair of substantially U-shaped cavities are filled with a source/drain material.Type: ApplicationFiled: January 4, 2017Publication date: July 5, 2018Inventors: Jianwei Peng, Hsien-Ching Lo, Suresh K. Regonda, Edward P. Reis, JR.
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Publication number: 20180151690Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.Type: ApplicationFiled: January 19, 2018Publication date: May 31, 2018Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
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Patent number: 9947769Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.Type: GrantFiled: November 29, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
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Patent number: 9887094Abstract: One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.Type: GrantFiled: May 3, 2017Date of Patent: February 6, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Yi Qi, Hsien-Ching Lo, Jianwei Peng, Yanping Shen, Hui Zhan
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Patent number: 9847225Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.Type: GrantFiled: November 15, 2011Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai Cheng, An-Shen Chang, Hui-Min Lin, Tsz-Mei Kwok, Hsien-Ching Lo
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Patent number: 9419101Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.Type: GrantFiled: November 4, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jianwei Peng, Hong Yu, Zhao Lun, Tao Han, Hsien-Ching Lo, Basab Banerjee, Wen Zhi Gao, Byoung-Gi Min
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Patent number: 8952459Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.Type: GrantFiled: August 20, 2013Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20130334617Abstract: A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka HING, Haiting WANG, Han-Ting TSAI, Chun-Fai CHENG, Wei-Yuan LU, Hsien-Ching LO, Kuan-Chung CHEN
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Patent number: 8535998Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: March 9, 2010Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Patent number: 8502316Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.Type: GrantFiled: February 11, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ka-Hing Fung, Han-Ting Tsai, Chun-Fai Cheng, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo
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Publication number: 20130119444Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai CHENG, An-Shen CHANG, Hui-Min LIN, Tsz-Mei KWOK, Hsien-Ching LO
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Patent number: 8368147Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: GrantFiled: April 16, 2010Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20110254105Abstract: A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan, Hsueh-Chang Sung, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Publication number: 20110223752Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: March 9, 2010Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fung Ka HING, Haiting WANG, Han-Ting TSAI, Chun-Fai CHENG, Wei-Yuan LU, Hsien-Ching LO, Kuan-Chung CHEN
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Publication number: 20110193167Abstract: An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ka-Hing Fung, Han-Ting Tsai, Chun-Fai Cheng, Haiting Wang, Wei-Yuan Lu, Hsien-Ching Lo