Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current to illuminate one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A display device includes a light emitting unit, first and second capacitors, and first and second switches. The light emitting unit emits light according to a voltage level of a first node. A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the light emitting unit. A first terminal of the first switch is coupled to the first node, and a second terminal of the first switch is coupled to the light emitting unit. The second switch is configured to be turned on before the first switch is turned on, and a first terminal of the second switch is coupled to the first node.

Abstract: A pixel driving device includes at least one data line and at least one driver integrated circuit. The at least one data line includes a first area and a second area on both sides. The first area and the second area are separated by the at least one data line. The at least one driver integrated circuit includes a first circuit and a second circuit. The first circuit is disposed in the first area, is configured to receive at least one first high-frequency signal so as to at least one first driving signal. The second circuit is disposed in the second area, is coupled to the first circuit and is configured to receive at least one low-frequency signal.

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.

Abstract: The present disclosure provides a light emitting diode component, including a body and a plurality of P-N diode structures. The P-N diode structures are coupled in series and integrated on the body. The P-N diode structures include a plurality of p-type doping layers and a plurality of n-type doping layers. The p-type doping layer of a first P-N diode structure in the P-N diode structures is electrically coupled to the n-type doping layer of a second P-N diode structure in the P-N diode structures.

Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.

Abstract: The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting element. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting element is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.

Abstract: A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other.

Abstract: A display device includes a light emitting unit, first and second capacitors, and first and second switches. The light emitting unit emits light according to a voltage level of a first node. A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the light emitting unit. A first terminal of the first switch is coupled to the first node, and a second terminal of the first switch is coupled to the light emitting unit. The second switch is configured to be turned on before the first switch is turned on, and a first terminal of the second switch is coupled to the first node.

Abstract: A pixel driving device includes at least one data line and at least one driver integrated circuit. The at least one data line includes a first area and a second area on both sides. The first area and the second area are separated by the at least one data line. The at least one driver integrated circuit includes a first circuit and a second circuit. The first circuit is disposed in the first area, is configured to receive at least one first high-frequency signal so as to at least one first driving signal. The second circuit is disposed in the second area, is coupled to the first circuit and is configured to receive at least one low-frequency signal.

Abstract: A shift register circuit includes a driving signal generating circuit, a coupling circuit, and a sweep signal generating circuit. The driving signal generating circuit is configured to receive a plurality of first clock signals, a low voltage source, an initial signal, and a first high voltage source so as to output a driving signal. The coupling circuit is coupled to the driving signal generating circuit. The coupling circuit is configured to transmit the low voltage source. The sweep signal generating circuit is coupled to the coupling circuit. The sweep signal generating circuit is configured to receive a second clock signal, the low voltage source, and a second high voltage source so as to output a sweep signal. A waveform of the sweep signal includes an oblique waveform. The first high voltage source and the second high voltage source are electrically independent of each other.

Abstract: A display device includes a pixel driving circuit including a data writing unit, a light emitting unit and a compensation unit. The data writing unit includes first and second capacitors. A first terminal of the first capacitor is coupled to a first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the first node. The light emitting unit includes a first switch and a light emitting element. A control terminal of the first switch is coupled to the second node, and a first terminal of the first switch is coupled to a second terminal of the second capacitor. The compensation unit includes a second switch. The second switch is coupled to the second node and a second terminal of the first switch.

Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current to illuminate one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.