Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: A light emitting diode (LED) display apparatus includes first to third data lines, gate lines, a first color sub-pixel unit and second color sub-pixel units. The gate lines include (N?1)th, Nth and (N+1)th gate lines. The first color sub-pixel unit includes a first color LED electrically coupled to the first data line and the (N?1)th and Nth gate lines. When the (N?1)th or Nth gate line is enabled, the first color LED is turned on. The second color sub-pixel unit is electrically connected to the second data line, and includes a second color LED. The second color sub-pixel units are electrically coupled to the gate lines, respectively. When each gate line is enabled, the corresponding second color LED is turned on. A light emitting area of the first color sub-pixel unit is greater than a light emitting area of each second color sub-pixel unit.

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: Each Multi-domain Vertical Alignment (MVA) pixel structures on a display panel array includes at least two sub-pixels. By adjusting the channel W/L ratios of the transistors in the sub-pixels, the sub-pixels may have different display voltages so as to improve the display quality in a slant vision. A transistor is disposed between one of the sub-pixels and a common line (Vcs) as the dispersion path for remaining electric charges to improve the condition of burn-in.

Abstract: A pixel circuit and a driving method thereof are provided. The pixel circuit includes a pixel capacitor, a storage capacitor, a first transistor and a second transistor. A common node is between the storage capacitor and the pixel capacitor. The first transistor is electrically connected between a data line and the common node, and a gate thereof is electrically connected to a first gate line. The second transistor is electrically connected between the common node and a gray level voltage, and a gate thereof is electrically connected to a second gate line. The first gate and the second gate line are adjacent.

Abstract: Each Multi-domain Vertical Alignment (MVA) pixel structures on a display panel array includes at least two sub-pixels. By adjusting the channel W/L ratios of the transistors in the sub-pixels, the sub-pixels may have different display voltages so as to improve the display quality in a slant vision. A transistor is disposed between one of the sub-pixels and a common line (Vcs) as the dispersion path for remaining electric charges to improve the condition of burn-in.

Abstract: A flat panel display is provided. The flat panel display includes a display panel, a gate driver, a source driver and a signal switching unit. The gate driver outputs a gate signal. The signal switching unit turns on the first terminal and the second terminal thereof to deliver the gate signal to a first scan line during a preceding half period of a frame period. Moreover, the signal switching unit turns on the first terminal and the third terminal thereof during a rear half period of the frame period, so that the gate signal, which is previously delivered to the first scan line, is delivered to the second scan line at this time. In this way, the source driver drives the display panel in coordination with the gate signal delivered by the first and second scan lines.

Abstract: A pixel structure includes a scan line, a data line, a first thin film transistor (TFT), a second TFT, a first pixel electrode, a second pixel electrode and a third pixel electrode. The first TFT and the second TFT respectively possessing a first drain electrode and a second drain electrode are electrically connected to the scan line and the data line. The first pixel electrode is electrically connected to the first drain electrode. The second pixel electrode is placed on and coupled to parts of the first drain electrode, and the third pixel electrode is placed on and coupled to parts of the second drain electrode. As a result, the pixel structure is capable of reducing display quality variations arisen from different viewing angles.