Abstract: A manufacturing method of miniature fluid actuator is disclosed and includes the following steps. A flow-channel main body manufactured by a CMOS process is provided, and an actuating unit is formed by a deposition process, a photolithography process and an etching process. Then, at least one flow channel is formed by etching, and a vibration layer and a central through hole are formed by a photolithography process and an etching process. After that, an orifice layer is provided to form at least one outflow opening by an etching process, and then a chamber is formed by rolling a dry film material on the orifice layer. Finally, the orifice layer and the flow-channel main body are flip-chip aligned and hot-pressed, and then the miniature fluid actuator is obtained by a flip-chip alignment process and a hot pressing process.

Abstract: A miniature fluid actuator is disclosed and includes a substrate, a chamber layer, a carrying layer and a piezoelectric assembly. The substrate has an inlet. The chamber layer is formed on the substrate and includes a first chamber in communication with the inlet, a resonance layer and a second chamber. The resonance layer has a central aperture in communication between the first chamber and the second chamber. The carrying layer includes a fixed region formed on the chamber layer, a vibration region, a connection portion and a vacant. The vibration region is located at a center of the fixed region and corresponding to the second chamber. The connection portion is connected between the fixed region and the vibration region. The vacant is formed among the fixed region, the vibration region and the connection portion. The piezoelectric assembly is formed on the vibration region.

Abstract: A wafer structure is disclosed and includes a chip substrate and an inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the inkjet chip. The inkjet chip includes plural ink-drop generators generated by the semiconductor process on the chip substrate. Each of the plurality of ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and plural horizontal axis array groups having a central stepped pitch equal to or less than 1/600 inches.

Abstract: A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

Abstract: A wafer structure including a chip substrate and plural inkjet chips is disclosed. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of at least 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the first inkjet chip and the second inkjet chip. Each of the first inkjet chip and the second inkjet chip includes plural ink-drop generators. Each of the ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and form plural horizontal axis array groups having a central stepped pitch equal to 1/600 inches or less.

Abstract: A wafer structure is disclosed and includes a chip substrate and plural inkjet chips having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process. At least one inkjet chip is directly formed on the chip substrate by the semiconductor process and diced into the at least one inkjet chip for inkjet printing. Each of the inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

Abstract: A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process. The inkjet chip is directly formed on the chip substrate by the semiconductor process, whereby the wafer structure is diced, and the inkjet chip is produced, to be implemented for inkjet printing. The inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a barrier layer, an ink-supply chamber and a nozzle, and the ink-supply chamber and the nozzle are integrally formed in the barrier layer.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of at least 12 inches. The inkjet chips include at least one first inkjet chip and at least one second inkjet chip directly formed on the chip substrate by the semiconductor process, respectively, and the plurality of inkjet chips are diced into the at least one first inkjet chip and the at least one second inkjet chip for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by a semiconductor process and formed on the chip substrate. Each of the ink-drop generators includes a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle.

Abstract: A wafer structure is disclosed and includes a chip substrate and at least one inkjet chip. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The at least one inkjet chip is directly formed on the chip substrate by the semiconductor process, and the wafer is diced into the at least one inkjet chip, to be implemented for inkjet printing.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each ink-drop generator includes a barrier layer, an ink-supply chamber and a nozzle. The ink-supply chamber and the nozzle are integrally formed in the barrier layer.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate.

Abstract: A manufacturing method of micro fluid actuator includes: providing a substrate; depositing a first protection layer on a first surface of the substrate; depositing an actuation region on the first protection layer; applying lithography dry etching to a portion of the first protection layer to produce at least one first protection layer flow channel; applying wet etching to a portion of a main structure of the substrate to produce a chamber body and a first polycrystalline silicon flow channel region, while a region of an oxidation layer middle section of the main structure is not etched; applying reactive-ion etching to a portion of a second surface of the substrate to produce at least one substrate silicon flow channel; and applying dry etching to a portion of a silicon dioxide layer to produce at least one silicon dioxide flow channel.

Abstract: A gas detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a light-emitting element, a particle-sensing element, a gas-sensing element, a driving-chip element and an encapsulation layer. The driving-chip element controls driving operations of the microelectromechanical element, the light-emitting element, the particle-sensing element and the gas-sensing element, respectively. When the microelectromechanical element is enabled to actuate transportation of gas, the gas is introduced into the gas detection device through an inlet aperture of the substrate. Scattered light spots generated by the light beam of the light-emitting element irradiating on suspended particles contained in the gas are received by the particle-sensing element to generate a detection datum of the suspended particles. The gas-sensing element detects the gas passing through and generates a detection datum of hazardous gas contained in the gas.

Abstract: A micro fluid actuator includes an orifice layer, a flow channel layer, a substrate, a chamber layer, a vibration layer, a lower electrode layer, a piezoelectric actuation layer and an upper electrode layer, which are stacked sequentially. An outflow aperture, a plurality of first inflow apertures and a second inflow aperture are formed in the substrate by an etching process. A storage chamber is formed in the chamber layer by the etching process. An outflow opening and an inflow opening are formed in the orifice layer by the etching process. An outflow channel, an inflow channel and a plurality of columnar structures are formed in the flow channel layer by a lithography process. By providing driving power which have different phases to the upper electrode layer and the lower electrode layer, the vibration layer is driven to displace in a reciprocating manner, so as to achieve fluid transportation.

Abstract: A MEMS pump includes a first substrate, a first oxide layer, a second substrate, a second oxide layer, a third substrate and a piezoelectric element sequentially stacked to form the entire structure of the MEMS pump. The first substrate has a first thickness and at least one inlet aperture. The first oxide layer has at least one fluid inlet channel and a convergence chamber, wherein the fluid inlet channel communicates with the convergence chamber and the inlet aperture. The second substrate has a second thickness and a through hole, and the through hole is misaligned with the inlet aperture and communicates with the convergence chamber. The second oxide layer has a first chamber with a concave central portion. The third substrate has a third thickness and a plurality of gas flow channels, wherein the gas flow channels are misaligned with the through hole.

Abstract: A micro channel structure includes a substrate, a supporting layer, a valve layer, a second insulation layer, a vibration layer and a bonding-pad layer. A flow channel is formed on the substrate. A conductive part and a movable part are formed on the supporting layer and the valve layer, respectively. A first chamber is formed at the interior of a base part and communicates to the hollow aperture. A supporting part is formed on the second insulation layer. A second chamber is formed at the interior of the supporting layer and communicates to the first chamber through the hollow aperture. A suspension part is formed on the vibration layer. By providing driving power sources having different phases to the bonding-pad layer, the suspension part moves upwardly and downwardly, and a relative displacement is generated between the movable part and the conductive part, to achieve fluid transportation.

Abstract: A micro-electromechanical systems pump includes a first substrate, a first oxide layer, a second substrate, and a piezoelectric element. The first oxide layer is stacked on the first substrate. The second substrate is combined with the first substrate, and the second substrate includes a silicon wafer layer, a second oxide layer, and a silicon material layer. The silicon wafer layer has an actuation portion. The actuation portion is circular and has a maximum stress value and an actuation stress value. The second oxide layer is formed on the silicon wafer layer. The silicon material layer is located at the second oxide layer and is combined with the first oxide layer. The piezoelectric element is stacked on the actuation portion, and has a piezoelectric stress value. The maximum stress value is greater than the actuation stress value, and the actuation stress value is greater than the piezoelectric stress value.

Abstract: A narrow type inkjet print head chip is disclosed and includes a silicon substrate, an active component layer and a passive component layer. The active component layer is stacked on the silicon substrate and includes plural ESD protection units, plural encoder switches, plural discharge protection units and plural heater switches. The ESD protection units, the encoder switches, the discharge protection units and the heater switches are disposed in each of at least two high-precision regions of the active component layer. The corresponding positions and quantities of these components are the same in the at least two high-precision regions. The passive component layer is stacked on the active component layer and includes plural heaters, plural electrode pads, plural encoders and plural circuit traces. The circuit traces are electrically connected to the ESD protection units, the encoder switches, the heater switches, the heaters, the electrode pads and the encoders.