Patents by Inventor HSIEN-JU TSOU
HSIEN-JU TSOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071849Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
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Patent number: 11855003Abstract: A method of fabricating an integrated fan-out package is provided. A ring-shaped dummy die and a group of integrated circuit dies are mounted over a carrier, wherein the group of integrated circuit dies are surrounded by the ring-shaped dummy die. The ring-shaped dummy die and the group of integrated circuit dies over the carrier are encapsulated with an insulating encapsulation. A redistribution circuit structure is formed on the ring-shaped dummy die, the group of integrated circuit dies and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the group of integrated circuit dies, and the ring-shaped dummy die is electrically floating.Type: GrantFiled: May 13, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Hsien-Ju Tsou
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Publication number: 20230020959Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Hsien-Ju TSOU, Chih-Wei WU, Ying-Ching SHIH, Szu-Wei LU
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Publication number: 20220367383Abstract: A method of fabricating an integrated fan-out package is provided. A ring-shaped dummy die and a group of integrated circuit dies are mounted over a carrier, wherein the group of integrated circuit dies are surrounded by the ring-shaped dummy die. The ring-shaped dummy die and the group of integrated circuit dies over the carrier are encapsulated with an insulating encapsulation. A redistribution circuit structure is formed on the ring-shaped dummy die, the group of integrated circuit dies and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the group of integrated circuit dies, and the ring-shaped dummy die is electrically floating.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Hsien-Ju Tsou
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Patent number: 11456245Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.Type: GrantFiled: September 25, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsien-Ju Tsou, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
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Patent number: 11296032Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.Type: GrantFiled: May 28, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hsien-Ju Tsou, Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu
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Publication number: 20220077108Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Hsien-Ju Tsou
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Patent number: 11205615Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.Type: GrantFiled: September 13, 2019Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
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Publication number: 20210375768Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Hsien-Ju TSOU, Chih-Wei WU, Ying-Ching SHIH, Szu-Wei LU
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Publication number: 20210375741Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.Type: ApplicationFiled: September 25, 2020Publication date: December 2, 2021Inventors: Hsien-Ju TSOU, Chih-Wei WU, Ying-Ching SHIH, Szu-Wei LU
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Patent number: 11183482Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.Type: GrantFiled: September 17, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Hsien-Ju Tsou
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Patent number: 11164855Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.Type: GrantFiled: September 17, 2019Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
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Patent number: 11139285Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.Type: GrantFiled: November 20, 2019Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
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Publication number: 20210082870Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Hsien-Ju Tsou
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Publication number: 20210082894Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
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Patent number: 10916450Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.Type: GrantFiled: November 29, 2018Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
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Patent number: 10879194Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.Type: GrantFiled: May 25, 2017Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Jeh-Yin Chang, Li-Chung Kuo, Hsien-Ju Tsou, Yi Chou, Ying-Ching Shih, Szu-Wei Lu
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Publication number: 20200091131Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.Type: ApplicationFiled: November 20, 2019Publication date: March 19, 2020Inventors: HSIEN-JU TSOU, CHIH-WEI WU, PU WANG, YING-CHING SHIH, SZU-WEI LU, JING-CHENG LIN
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Patent number: 10586763Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.Type: GrantFiled: April 30, 2018Date of Patent: March 10, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
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Publication number: 20200006225Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih