Patents by Inventor HSIEN-JU TSOU

HSIEN-JU TSOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510732
    Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 10497690
    Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Publication number: 20190148288
    Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 16, 2019
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 10269589
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Publication number: 20190103387
    Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.
    Type: Application
    Filed: December 27, 2017
    Publication date: April 4, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
  • Publication number: 20190096868
    Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: HSIEN-JU TSOU, CHIH-WEI WU, PU WANG, YING-CHING SHIH, SZU-WEI LU, JING-CHENG LIN
  • Publication number: 20190096700
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Publication number: 20190006199
    Abstract: A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.
    Type: Application
    Filed: September 6, 2017
    Publication date: January 3, 2019
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Szu-Wei Lu, Ying-Ching Shih, Jing-Cheng Lin
  • Publication number: 20180342466
    Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: JING-CHENG LIN, LI-HUI CHENG, PO-HAO TSAI, JEH-YIN CHANG, LI-CHUNG KUO, HSIEN-JU TSOU, YI CHOU, YING-CHING SHIH, SZU-WEI LU