Patents by Inventor Hsien Lin

Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9838171
    Abstract: Methods of data allocation and signal receiving, a wireless transmitting apparatus, and a wireless receiving apparatus are provided based on orthogonal frequency division multiplexing (OFDM) technology. The wireless transmitting apparatus obtains a data stream and allocates the data stream to a first sub-carrier set. Each of the first sub-carrier set and a second sub-carrier set has sub-carriers with opposite frequencies to each other, respectively. The second sub-carrier is emptied or allocated according the data stream allocated to the first sub-carrier set. The data stream is converted into an OFDM signal transmitted through a transmitting module. The wireless receiving apparatus includes a single branch receiver for receiving a radio frequency (RF) signal and outputting a baseband signal. Subsequently, the data stream is restored from the baseband signal.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 5, 2017
    Assignee: Acer Incorporated
    Inventors: Tsung-Yu Tsai, You-Hsien Lin, Hsuan-Li Lin, Terng-Yin Hsu
  • Patent number: 9833195
    Abstract: A biomedical signal sensing circuit including a first and a second modulation unit, an amplifying unit, a first and a second demodulation unit is provided. The first modulation unit performs a first modulation operation to a first biomedical signal according to a first signal to generate a first modulation signal. The second modulation unit performs a second modulation operation to a second biomedical signal according to a second signal to generate a second modulation signal. The amplifying unit amplifies the first and second modulation signals, and adds the amplified first and second modulation signals to generate a third modulation signal. The first demodulation unit performs a first demodulation operation to the third modulation signal according to the first signal to generate a first sensing signal. The second demodulation unit performs a second demodulation operation to the third modulation signal according to the second signal to generate a second sensing signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: December 5, 2017
    Assignee: National Taiwan University
    Inventors: Yi-Lin Tsai, Fong-Wen Lee, Chih-Chan Tu, Bang-Cyuan Wang, Tsung-Hsien Lin
  • Publication number: 20170345930
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 30, 2017
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Publication number: 20170345383
    Abstract: A display panel subsystem adaptively employs one of three types of input offset voltage cancellation modes based on an analysis of gray level values of sub-pixels for each row un a frame of image data. The system selects a candidate row within a selected group of rows and applies a first chopper mode to each sub-pixel in the candidate row. Under a row-based mode, the system applies a second chopper mode to each sub-pixel included in a row having gray level values matching the candidate row. Under a per-column row-based mode, the system applies the row-based mode on a per-column basis. Under a sub-pixel-wise mode, for each column, the system changes a chopper mode applied to a sub-pixel in a subsequent row relative to the last state of the chopper mode in a row having the same gray level value as a corresponding sub-pixel in the subsequent row.
    Type: Application
    Filed: May 25, 2016
    Publication date: November 30, 2017
    Inventors: YOU-BEN YIN, YONG-NIEN RAO, HUA QIN, CHIA-HSIEN LIN
  • Publication number: 20170344067
    Abstract: A pivot structure includes a base, a bracket, an elastic component, and a positioning assembly. The bracket is rotatably connected to the base. The elastic component is disposed on the base. The positioning assembly includes an elastic clip and a pillar. The elastic clip is pivoted to the base and has a first releasing segment and a first positioning segment. The pillar is connected to the bracket and has a second positioning segment. The pillar is rotatably clipped in the elastic clip. The bracket is adapted to be expanded to a first expanding state through an elastic force of the elastic component, so as to drive the second positioning segment to move along the first releasing segment. The bracket is adapted to receive an external force to be further expanded to a second expanding state, so as to drive the second positioning segment to move to the first positioning segment.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 30, 2017
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Hao Lan, Jyh-Chyang Tzou, Ching-Tai Chang, Chia-Chi Lin, Tsai-Yu Lin, Hsin Yeh, Che-Hsien Lin, Cheng-Shiue Jan
  • Publication number: 20170345801
    Abstract: A display apparatus and a fabricating method thereof are provided. The display apparatus includes a substrate, a light emitting diode, a first bump, a first insulating layer and a second insulating layer. The light emitting diode has a first surface and a second surface opposite each other, wherein the first surface faces the substrate. The light emitting diode is bonded to the substrate through the first bump. The first insulating layer is disposed on a periphery of the first bump and the light emitting diode, and contacts the first bump and the first surface. The second insulating layer is disposed on the substrate and surrounds at least a portion of the first insulating layer.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Applicants: Innolux Corporation, Advanced Optoelectronic Technology Inc.
    Inventors: Chun-Hsien Lin, Tsau-Hua Hsieh, Po-Min Tu, Tzu-Chien Hung, Chien-Chung Peng, Shih-Cheng Huang
  • Publication number: 20170338211
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Application
    Filed: April 13, 2017
    Publication date: November 23, 2017
    Applicant: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • Publication number: 20170336835
    Abstract: A pivot structure assembly including a fixed cover and a hinge module is provided. The hinge module includes a torque element, a first shaft, a second shaft, a first bracket and a second bracket. The torque element is fixed on the fixed cover and has a first and a second axle sleeves, parallely disposed at two opposite sides of the torque element. The first shaft is disposed through the first axle sleeve, and the second shaft is disposed through the second axle sleeve. The first bracket is pivotally disposed on the torque element through the first shaft, and the second bracket pivotally disposed on the torque element through the second shaft. When the first and second brackets rotate relatively to the torque element, the first and second axle sleeves respectively provide different friction forces to the first and second shafts. In addition, an electronic device is also mentioned.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 23, 2017
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Hong-Tien Wang, Po-Hsiang Hu
  • Publication number: 20170337870
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 23, 2017
    Applicant: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Patent number: 9825144
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Patent number: 9818694
    Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsien Lin, Anthony Oates
  • Patent number: 9811000
    Abstract: A photolithography tool includes at least one process chamber, at least one front opening unified pod (FOUP) stage, at least one moving mechanism, and an image sensor. The moving mechanism is configured to move the wafer from the process chamber to the FOUP stage. The image sensor is configured to capture the image of the wafer on the moving mechanism.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Feng Liao, Chun-Hsien Lin, Pei-Yi Su, Yi-Ming Dai, Chung-Hsing Lee, Chien-Ko Liao, Chun-Yung Chang, Nan-Jung Chen, Pei-Yuan Wu, Hsien-Mao Huang
  • Patent number: 9804775
    Abstract: A method for managing user interface of an electronic device includes detecting touch points on a back panel of the electronic device within a predetermined time interval when the electronic device is unlocked. When a first number of the detected touch points on a left part of a back panel is more than a second number of the detected touch points on a right part of the back panel, icons are displayed on a right part of a display device of the electronic device. When a first number of the detected touch points on the left part of the back panel is less than the second number of the detected touch points on the right part of the back panel, the icons are displayed on a left part of the display device.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 31, 2017
    Assignee: FIH (HONG KONG) LIMITED
    Inventors: Yu-Hsien Lin, Hung-Ling Wei
  • Publication number: 20170309718
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20170309537
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170309722
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Patent number: 9799567
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 9799337
    Abstract: A microphone apparatus is provided. Whether an electronic signal converted from an audio signal is in compliance with a preset sound characteristic and a preset voice recognition information is determined. When the electronic signal is in compliance with the preset sound characteristic and the preset voice recognition information, an actuation control signal is outputted, so as to trigger an operation of an external circuit external to the microphone apparatus.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 24, 2017
    Assignee: MERRY ELECTRONICS(SUZHOU) CO., LTD.
    Inventors: Chao-Sen Chang, Shen-Hang Wei, You-Hsien Lin, Yung-Shiang Chang
  • Publication number: 20170301670
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Publication number: 20170301658
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen