Abstract: A sexual stimulating system with feedback control includes a physiological sensor, a sexual stimulator, and a processing module. The physiological sensor measures a physiological response of a user under sexual stimulation, and generates a sensor signal according to a result of the measurement of the physiological response. The sexual stimulator applies the sexual stimulation. The processing module is electrically connected to the physiological sensor and the sexual stimulator, receives the sensor signal, performs an analytical procedure upon the sensor signal for generating digital data, and generates a driving signal according to the digital data to control a degree of the sexual stimulation.

Abstract: A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract: A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.

Abstract: Glycosphingolipids (GSLs) bearing ?-glucose (?-Glc) that preferentially stimulate human invariant NKT (iNKT) cells are provided. GSLs with ?-glucose (?-Glc) that exhibit stronger induction in humans (but weaker in mice) of cytokines and chemokines and expansion and/or activation of immune cells than those with ?-galactose (?-Gal) are disclosed. GSLs bearing ?-glucose (?-Glc) and derivatives of ?-Glc with F at the 4 and/or 6 positions are provided. Methods for iNKT-independent induction of chemokines by the GSL with ?-Glc and derivatives thereof are disclosed. Methods for immune stimulation in humans using GSLs with ?-Glc and derivatives thereof are provided.

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.

Abstract: Reliable, scalable, and tunable SERS substrates are developed for quantitative SERS measurements and the limit of detection (LOD) can be down to single molecule level. This is achieved by the precise control of SERS enhancement factor and detection hot zone using ligand-regulated nanoparticle superlattices film with a built-in internal standard. The establishment of quantitative SERS technique will open up many exciting opportunities for both fundamental and applied research areas.

Abstract: A manufacturing method for a thin film device with separable carrier consisting of the following steps: First, preparing a mold release layer made from a polypropylene material. Next, preparing a carrier layer made from a polyethylene material, and then separably laminating the mold release layer onto a surface of the carrier layer to obtain a top-bottom laminated separable carrier. Next, coating a low-hardness material onto the other surface of the carrier layer to obtain a thin film substrate with a lamination of the separable carrier. Finally, separating the mold release layer on the thin film substrate from the carrier layer to obtain the thin film device.

Abstract: In accordance with some embodiments, a wafer taping device is provided. The wafer taping device includes a tape delivering along a first direction. The wafer taping device also includes a wafer mount unit disposed below the tape. The wafer mount unit has an upper surface for supporting a wafer and having a notch for allowing a cut mark of the wafer to align with it. The notch is staggered with a second direction in the upper surface, and the second direction is substantially perpendicular to the first direction. In addition, the wafer taping device includes a laminating roller disposed above the wafer mount unit and having a long axis elongated in the second direction. The laminating roller is configured to reciprocate along the first direction for pressing the tape to the wafer.

Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.

Abstract: A microphone apparatus is provided. Whether an electronic signal converted from an audio signal is in compliance with a preset sound characteristic and a preset voice recognition information is determined. When the electronic signal is in compliance with the preset sound characteristic and the preset voice recognition information, an actuation control signal is outputted, so as to trigger an operation of an external circuit external to the microphone apparatus.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Abstract: The present invention provides a positioning device configured to position a glass substrate. The positioning device comprises a support base, a pair of first positioning mechanisms located on two neighboring sides of the glass substrate, a pair of second positioning mechanisms located on another two neighboring sides of the glass substrate, respectively, a pair of connecting bars, a driving member, a gear group and a conveying belt sleeved on the gear group. One end of the one of the pair of connecting bar is fixed with the conveying belt, and another end is fixed with one of the pair of first positioning mechanisms. One end of another one of the pair of connecting bar is fixed with the conveying belt, and another end is fixed with another one of the pair of first positioning mechanisms.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure at least partially in a semiconductor substrate. The semiconductor device structure also includes a channel structure over the semiconductor substrate. The source structure is partially covered by the channel structure. The semiconductor device structure further includes a drain structure covering the channel structure. The drain structure and the source structure have different conductivity types. A portion of the channel structure is sandwiched between the source structure and the drain structure. In addition, the semiconductor device structure includes a gate stack partially covering the channel structure.

Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure at least partially in a semiconductor substrate. The semiconductor device structure also includes a channel structure over the semiconductor substrate. The source structure is partially covered by the channel structure. The semiconductor device structure further includes a drain structure covering the channel structure. The drain structure and the source structure have different conductivity types. A portion of the channel structure is sandwiched between the source structure and the drain structure. In addition, the semiconductor device structure includes a gate stack partially covering the channel structure.

Abstract: A wearable action-aware device is disclosed. The wearable action-aware device includes a clothing body, a signal receiving and computing element, and a conductive line made of conductive fabric. Two ends of the conductive line are electrically connected to the signal receiving and computing element, respectively, to form a circuit, and both the signal receiving and computing element and the conductive line are disposed on the clothing body. An exposed side of the conductive line has electrical conductivity, and the circuit is disposed on a part of the clothing body corresponding to a part of a body that needs to be measured. Action information of a user can be measured when the user wears the present invention wearable action-aware device.