Abstract: A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.

Abstract: A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mth stage scan signal of the 1st to Nth stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.

Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.

Abstract: A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Abstract: A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Abstract: A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Abstract: A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mth stage scan signal of the 1st to Nth stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.

Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.

Abstract: A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers. The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.

Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Abstract: A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers, The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.

Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

Abstract: A liquid crystal display (LCD) panel comprises a thin film transistor (TFT) array substrate, a color filter substrate and a sealant and a liquid crystal layer. The color filter substrate is disposed on the TFT array substrate. The sealant and a liquid crystal layer are arranged between the TFT array substrate and the color filter substrate, wherein the TFT array substrate includes a pixel structure having a metal layer, a first isolation layer, a first pixel electrode layer, a second pixel electrode layer, and a common electrode layer, the first isolation layer is disposed on the metal layer, the first isolation layer and the common electrode layer directly contact each other, and the first and the second pixel electrode layers are in a pixel unit area.

Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.