Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.

Abstract: The disclosure provides an anti-lock brake device including an oil pressure tank, a valve, and a movable component. The oil pressure tank has an accommodation space, an oil inlet channel, and an oil outlet channel connected to the accommodation space. The valve is slidably located in the oil inlet channel and for sealing or opening an oil inlet of the oil inlet channel. The movable component is located in the accommodation space and has a connecting channel corresponding to the oil inlet and an oil outlet of the oil outlet channel. When the movable component is slid to a depressurized position, the movable component is moved away from the valve for sealing the oil inlet, a first volume is produced between the connecting channel and the oil inlet, and a second volume, smaller than the first volume, is removed from between the connecting channel and the oil outlet.

Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: Non-human animals comprising a human or humanized IL-4 and/or IL-4R? nucleic acid sequence are provided. Non-human animals that comprise a replacement of the endogenous IL-4 gene and/or IL-4R? gene with a human IL-4 gene and/or IL-4R? gene in whole or in part, and methods for making and using the non-human animals, are described. Non-human animals comprising a human or humanized IL-4 gene under control of non-human IL-4 regulatory elements is also provided, including non-human animals that have a replacement of non-human IL-4-encoding sequence with human IL-4-encoding sequence at an endogenous non-human IL-4 locus. Non-human animals comprising a human or humanized IL-4R? gene under control of non-human IL-4R? regulatory elements is also provided, including non-human animals that have a replacement of non-human IL-4R?-encoding sequence with human or humanized IL-4R?-encoding sequence at an endogenous non-human C IL-4R? locus.

Abstract: The present invention is directed to an obstacle avoidance system for an unmanned vehicle, comprising: an obstacle sensing module provided at a vehicle body; a vehicle-mounted computer provided at the vehicle body and electrically connected to the obstacle sensing module; a control module provided at the vehicle body and electrically connected to the vehicle-mounted computer; and a power source provided at the vehicle body and electrically connected to the obstacle sensing module, the vehicle-mounted computer and the control module.

Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A gear module includes a rotating cylinder, a first planetary gear set, a second planetary gear set, a concave-convex structure, and a limit bearing set. The first planetary gear set is accommodated in the rotating cylinder and includes a driven gear; the second planetary gear set includes a positioning frame, second planetary gears pivoted to a positioning frame, a driven gear engaged with the second planetary gears, and the positioning frame has a through hole; the concave-convex structure includes a convex column extended from the rotating cylinder and a concave hole formed on the positioning frame, the convex column is plugged into the concave hole; the limit bearing set includes a first ball bearing sheathing the driven gear and mounted between the driven gear and the through hole, and a second ball bearing sheathing the convex column and mounted between the convex column and the concave hole.

Abstract: A method and a system for mental index prediction are provided. The method includes the following steps. A plurality of images of a subject person are obtained. A plurality of emotion tags of the subject person in the images are analyzed. A plurality of integrated emotion tags in a plurality of predetermined time periods are calculated according to the emotion tags respectively corresponding to the images. A plurality of preferred features are determined according to the integrated emotion tags. A mental index prediction model is established according to the preferred features to predict a mental index according to the emotional index prediction model.

Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.

Abstract: An aerial vehicle including a body, a first ranging device, a second ranging device and a controller is provided. The first ranging device is disposed on the body and is configured to detect a first distance between the first ranging device and the reflector. The second ranging device is disposed on the body and is configured to detect a second distance between the second ranging device and the reflector. The controller is configured to obtain an included angle between a direction of the body and the reflector according to the first distance and the second distance.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.