Abstract: Vertically stacked semiconductor devices and methods of fabrication thereof that include a first semiconductor die bonded to a second device structure in a face-down configuration, a gap fill dielectric layer laterally surrounding the first semiconductor die, and a recess fill dielectric layer formed over the gap fill dielectric layer to fill concave recess defects in the gap fill dielectric that may result from cracks in the first semiconductor die. The recess fill dielectric layer may fill the entire volume of one or more concave recess defects in the gap fill dielectric material to a vertical depth of 5 ?m or more below the backside surface of a semiconductor substrate of the first semiconductor die. Providing a recess fill dielectric layer within concave recess defects in the gap fill dielectric layer may result in enhanced protection against electrical arcing during subsequent processing steps and thereby provide improved device yields.

Abstract: A semiconductor package with two interposers, and the method of forming the same are provided. The semiconductor package may include a first interposer, a first semiconductor die on the first interposer, a second interposer on the first semiconductor die, and a second semiconductor die on the second interposer. The second interposer may be between the first semiconductor die and the second semiconductor die. The first semiconductor die may be bonded to the first interposer by metal-to-metal bonding and dielectric-to-dielectric bonding. The second semiconductor die may be bonded to the second interposer by metal-to-metal bonding and dielectric-to-dielectric bonding.

Abstract: First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.

Abstract: An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material. Embodiments include methods of fabricating the integrated passive dies.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first die, and a second die disposed aside of and spaced apart from the first die with a gap there-between, a molding compound wrapping the first and second dies, a redistribution layer disposed on the molding compound and the first and second dies, a passive component and a thermal dissipating component. A first portion of the molding compound is disposed within and filled in the gap. The passive component is disposed on the redistribution layer, and located above the first portion of the molding compound and across the gap. The thermal dissipating component is disposed on the redistribution layer and beside the passive component, separate and distanced from the passive component. The thermal dissipating component is located above a corner of at least one of the first and second semiconductor dies.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: A semiconductor package includes an interconnect structure, a plurality of dies disposed on the interconnect structure in a side-by-side manner, an underfill filling between the interconnect structure and the plurality of dies and filling a lower part of a gap between adjacent two of the plurality of dies, a conductive layer at least covering back surfaces of the adjacent two of the plurality of dies and filling an upper part of the gap, and an encapsulating material laterally encapsulating the plurality of dies and the conductive layer.

Abstract: A die structure is provided. The die structure includes a first semiconductor die, a second semiconductor die disposed over the first semiconductor die, a first bonding layer disposed over the second semiconductor die, a high-k layer disposed over the bonding layer, and a substrate disposed over the high-k layer. The compressive film stress of the first bonding layer is less than the compressive film stress of the high-k layer.

Abstract: A semiconductor structure and methods of making the same. In embodiments, the semiconductor device includes a redistribution layer. The redistribution layer includes a passivation layer and a via. Further, the semiconductor device includes a dielectric layer located above the passivation layer and a surface mount connector located above the via. In some embodiments, the surface mount connector may further be located above a portion of the dielectric layer. Additionally, the semiconductor device includes a metallic liner located between the surface mount connector and the redistribution layer.

Abstract: Semiconductor devices having dummy dies and methods of fabricating semiconductor devices with dummy dies. An embodiment semiconductor device includes an interconnect structure and one or more active devices attached to the interconnect structure, the one or more active devices being electrically connected to the interconnect structure through a plurality of conductive bumps. The semiconductor device includes a dummy die attached to the interconnect structure by an adhesive layer, wherein the adhesive layer comprises one of a die attach film (DAF) layer, a film over wire (FOW) layer, or a non-conductive film (NCF) layer.

Abstract: A die structure is provided. The die structure includes a base having a first device region and a second device region adjacent to the first device region. The die structure includes a plurality of first device cores stacked on the first device region of the base. The die structure includes a plurality of second device cores stacked on the second device region of the base. The die structure includes a top core over the first device cores and the second device cores. An interconnect structure is embedded in the top core and electrically connected to the first device cores and the second device cores. The die structure also includes a die molding material formed over the base and encapsulating the first device cores, the second device cores, and the top core.

Abstract: An embodiment semiconductor package assembly may include an interposer, an integrated passive device electrically coupled to a first side of the interposer, an underfill material portion formed between the integrated passive device and the first side of the interposer, and a dam protruding from the first side of the interposer and configured to constrain a spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer that also includes a component of a redistribution interconnect structure. The dam may further be electrically isolated from the redistribution interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.

Abstract: An information handling system motherboard add-in card slot accepts an add-in card that cooperates to process information, such as graphics processing card that generates pixel values for presentation at a display. An add-in card release couples to the motherboard near the add-in card slot with a lifting member aligned to apply a lifting force to remove the add-in card in response to a press by an actuator member displaced for better end user interactions. In one example embodiment, the lifting member has first and second arms on opposing sides of the add-in card slot rotationally coupled to a base. In an alternative embodiment, the lifting member has a pulley engaged with a wire that applies a lifting force when a push button actuator member is pressed.

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a protective layer to laterally surround an interconnection chip. The interconnection chip has a conductive via penetrating through a semiconductor substrate of the interconnection chip. The conductive via has a first portion and a second portion, and sidewall slopes of the first portion and the second portion are different. The second portion gradually becomes narrower along a direction towards the first portion. The method also includes forming a redistribution structure over the interconnection chip and the protective layer. The redistribution structure has multiple organic layers and multiple conductive features. The method further includes bonding a first chip-containing structure and a second chip-containing structure to the redistribution structure. Each of the first chip-containing structure and the second chip-containing structure partially covers the interconnection chip.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a redistribution structure disposed over the substrate, and a semiconductor die disposed over the redistribution structure. The redistribution structure includes a dielectric layer, a conductive feature formed in the dielectric layer, and a heat transfer feature formed in the dielectric layer and being electrically isolated from the conductive feature. The semiconductor die is electrically connected to the conductive feature. The semiconductor die partially overlaps the heat transfer feature from a top view.

Abstract: A die stack structure is provided. The die stack structure includes a non-extended semiconductor die, an extended semiconductor die, and an extended top semiconductor die are stacked vertically over a base semiconductor die. The extended semiconductor die and the extended top semiconductor die each have an extension portion extending horizontally outward from one side thereof as compared to the non-extended semiconductor die. An encapsulant layer is formed over the base semiconductor die and encapsulates the sidewalls of the non-extended semiconductor die, the extended semiconductor die, and the extended top semiconductor die. Thermally conductive features are formed in the extension portion of the extended semiconductor die and in the extension portion of extended top semiconductor die. A thermally conductive structure is embedded in the encapsulant layer, extending vertically between the extended semiconductor die and the extended top semiconductor die, and contacting the thermally conductive features.

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, a second semiconductor die, a first thermal interface material (TIM) film, a second TIM film, and a heat-dissipating lid. The redistribution layer is attached to the substrate. The first semiconductor die and the second semiconductor die are disposed over the redistribution layer. The first TIM film is formed over the first semiconductor die. The second TIM film is formed over the second semiconductor die. The heat-dissipating lid is attached to the substrate. The heat-dissipating lid has first regions with a first cavity depth and a second region with a second cavity depth. The second cavity depth is greater than the first cavity depth. The second TIM film is disposed in the second region of the heat-dissipating lid.