Patents by Inventor Hsien-Wei Chen

Hsien-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262771
    Abstract: A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220260776
    Abstract: A structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220262768
    Abstract: A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die.
    Type: Application
    Filed: February 12, 2021
    Publication date: August 18, 2022
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen
  • Publication number: 20220262772
    Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Patent number: 11417587
    Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11417599
    Abstract: Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Chia-Wei Tu
  • Patent number: 11418159
    Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 16, 2022
    Assignee: GRACE CONNECTION MICROELECTRONICS LIMITED
    Inventors: Pei Wei Chen, Hsien-Ku Chen
  • Patent number: 11417610
    Abstract: A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 11417619
    Abstract: A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh
  • Patent number: 11410956
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 11410948
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen
  • Publication number: 20220246524
    Abstract: A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.
    Type: Application
    Filed: March 2, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Publication number: 20220246573
    Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sen-Bor Jan, Sung-Feng Yeh
  • Publication number: 20220246502
    Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Patent number: 11404404
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure for optically coupling a fiber includes a photonic die, an electronic die disposed on and electrically coupled to the photonic die, and an insulating layer disposed on the photonic die and extending along sidewalls of the electronic die. The photonic die includes a first portion and a second portion connected to the first portion, an optical device of the photonic die optically coupled to the fiber is within the first portion, and the second portion extends beyond lateral extents of the first portion.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220238397
    Abstract: Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Publication number: 20220238484
    Abstract: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 28, 2022
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220230996
    Abstract: A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Publication number: 20220223564
    Abstract: A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.
    Type: Application
    Filed: May 7, 2021
    Publication date: July 14, 2022
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220223553
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.
    Type: Application
    Filed: May 10, 2021
    Publication date: July 14, 2022
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Jie Chen