Hsien-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.
Abstract: A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package.
Abstract: A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.
Abstract: A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.
Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.
Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
Abstract: A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row.
October 15, 2020
Date of Patent:
May 25, 2021
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: Provided is a semiconductor structure including a pad disposed over and electrically connected to an interconnect structure, wherein the pad has a probe mark, and the probe mark has a concave surface; a protective layer conformally covering the pad and the probe mark; and a bonding structure disposed over the protective layer, wherein the bonding structure includes: a bonding dielectric layer includes a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; a first bonding metal layer including a via plug and a metal feature, wherein the via plug penetrates through the first bonding dielectric material and the protective layer to electrically connect to the pad having the probe mark, the metal feature is located on the via plug and the first bonding dielectric material, and the metal feature is laterally surrounded by the second bonding dielectric material.
Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.
Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.
Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.
Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.
Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.
Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
Abstract: A resin composition is provided. The resin composition comprises the following components: (A) epoxy resin; (B) a cross-linking agent; (C) bismaleimide resin (BMI) represented by the following formula (I): wherein R1 is an organic group; and (D) a resin represented by the following formula (II): wherein n is an integer of 1 to 10.
Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.
Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
December 7, 2020
April 22, 2021
Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu
Abstract: A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.
December 17, 2019
Date of Patent:
April 13, 2021
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.