Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

Abstract: A semiconductor die includes an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section is connected to the first section. The second section is inclined with respect to a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

Abstract: A package includes a photonic integrated circuit die and an electric integrated circuit die. The photonic integrated circuit die includes a substrate and a waveguide. The substrate has a notch and the notch is occupied by air. The waveguide is disposed over the substrate. In a top view, a first portion of the waveguide is overlapped with the substrate and a second portion of the waveguide is overlapped with the notch. The electric integrated circuit die is disposed over the photonic integrated circuit die.

Abstract: A package has a first region and a second region encircled by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die is located in both the first region and the second region. The second die is bonded to the first die and is completely located within the first region. The encapsulant laterally encapsulates the second die. The encapsulant is located in both the first region and the second region. The inductor is completely located within the second region. A metal density in the first region is greater than a metal density in the second region.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an interposer over a substrate. A spacer structure is mounted to a bottom surface of the interposer. The spacer structure is configured to maintain a clearance between a bottom surface of an integrated circuit die mounted to the bottom surface of the interposer and a top surface of the substrate to reduce a likelihood of an interference or collision between the integrated circuit die and the substrate. In this way, a likelihood of damage to the integrated circuit die and/or the substrate is reduced. Additionally, a robustness of an electrical connection between the integrated circuit die and the interposer may increase to improve a reliability and/or a yield of the semiconductor package including the spacer structure.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.

Abstract: A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die.

Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

Abstract: A method includes forming a first package component, which includes an interposer, and a first die bonded to a first side of the interposer. A second die is bonded to a second side of the interposer. The second die includes a substrate, and a through-via penetrating through the substrate. The method further includes bonding a second package component to the first package component through a first plurality of solder regions. The first package component is further electrically connected to the second package component through the through-via in the second die. The second die is further bonded to the second package component through a second plurality of solder regions.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.

Abstract: A semiconductor package including a first die, a second die and a transparent encapsulation material is provided. The first die includes a first substrate and an optical coupler formed on the first substrate. The second die is disposed on the first die and includes a transparent portion overlapping the optical coupler. The transparent encapsulation material is disposed on the first die and laterally encapsulates the second die.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a dummy die disposed over the package component. The package structure includes a device die adjacent to the dummy die, and a buffer layer formed below the dummy die. The buffer layer has a first surface and an opposite second surface, the first surface is in direct contact with a bottom surface of the dummy die and the second surface is separated from the package component. The package structure includes a package layer surrounding the device die, the dummy die and the buffer layer.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.

Abstract: A package includes a photonic integrated circuit die, an electric integrated circuit die, and an encapsulant. The photonic integrated circuit die includes a semiconductor substrate and a waveguide. The semiconductor substrate has a notch. The waveguide is disposed over the semiconductor substrate. A portion of the waveguide is located within a span of the notch of the semiconductor substrate. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The encapsulant laterally encapsulates the electric integrated circuit die.