Patents by Inventor Hsin-Han Lin

Hsin-Han Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12349293
    Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: July 1, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Cheng Huang, I-Hung Chiang, Ji-Yuan Syu, Hsin-Han Lin, Po-Kai Chiu, Kuo-Shu Kao
  • Publication number: 20250210421
    Abstract: A power module with detachable function is provided. The power module includes a housing box part, a power component, a housing cover part, and a sensing component. The sensing component is configured to measure parameters of the power component and detachably installed on the housing cover part and the housing box part. When the housing cover part is mounted on the housing box part, the housing cover part and the housing box part can restrict the movement of the sensing component. Thus, a tight fit can be achieved.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 26, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Cheng LIU, Yuan-Cheng HUANG, Shian-Chiau CHIOU, Hsin-Han LIN, Chun-Kai LIU
  • Publication number: 20250035921
    Abstract: A defogging lens barrel structure includes a lens barrel, a heating module, and a lens assembly. The lens barrel includes a receiving groove with an inner wall. The heating module and the lens assembly are respectively disposed within the lens barrel. The lens assembly includes a first lens mounted in the receiving groove, supported by the heating module, and having a peripheral portion. A slot is provided between the peripheral portion and the inner wall. The receiving groove has a positioning part. The heating module has a positioned part correspondingly matching with the positioning part. A gap is provided between the heating module and the inner wall. With such design, the contact of the heating module and the first lens with the inner wall of the lens barrel could be reduced, thereby reducing the effect of the heat of the heating module and the first lens being dispersed.
    Type: Application
    Filed: December 26, 2023
    Publication date: January 30, 2025
    Applicant: Calin Technology Co., Ltd.
    Inventors: HSIN-HAN LIN, SUNG-CHIH WU
  • Publication number: 20240427111
    Abstract: A defogging lens barrel structure includes a lens barrel, a lens assembly, a heating module, a temperature-sensing module, and a thermal insulating material. The lens barrel has a receiving groove. An inner portion of the receiving groove includes an abutting surface and a recess disposed on the abutting surface. The lens assembly is disposed inside the lens barrel and includes a first lens disposed in the receiving groove. The first lens has a lens abutting surface correspondingly facing the abutting surface. The heating module is disposed between the abutting surface of the lens barrel and the lens abutting surface of the first lens and is adapted to provide a heat source. The temperature-sensing module is engaged with the heating module and is received in the recess of the lens barrel. The thermal insulating material encloses around the temperature-sensing module to be filled into the recess.
    Type: Application
    Filed: September 28, 2023
    Publication date: December 26, 2024
    Applicant: Calin Technology Co., Ltd.
    Inventors: HSIN-HAN LIN, SUNG-CHIH WU
  • Publication number: 20240243097
    Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 18, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, I-Hung Chiang, Chun-Kai Liu, Po-Kai Chiu, Hsin-Han Lin, Kuo-Shu Kao
  • Publication number: 20240154642
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Publication number: 20240130055
    Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.
    Type: Application
    Filed: March 2, 2023
    Publication date: April 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Cheng HUANG, I-Hung CHIANG, Ji-Yuan SYU, Hsin-Han LIN, Po-Kai CHIU, Kuo-Shu KAO
  • Patent number: 11876551
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shih-Wen Lu, Chun-Jen Chen, Po-Hsiang Tseng, Hsin-Han Lin, Ming-Lun Yu
  • Publication number: 20230352361
    Abstract: Provided are a power module and a manufacturing method thereof. The power module includes an insulating substrate, a first, a second and a third conductive layers, a first thermal interface material layer, a first and a second chips and a thermal conductive layer. The insulating substrate has a first and a second surfaces opposite to each other. The first and the second conductive layers are disposed on the first surface, and electrically separated from each other. The first thermal interface material layer is disposed on the first conductive layer. The third conductive layer is disposed on the first thermal interface material layer. The first chip is disposed on the third conductive layer and electrically connected to the third conductive layer. The second chip is disposed on the second conductive layer and electrically connected to the second conductive layer. The thermal conductive layer is disposed on the second surface.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Tai-Jyun Yu
  • Publication number: 20230057327
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Patent number: 11239168
    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 1, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Yu-Min Lin, Tao-Chih Chang
  • Publication number: 20210035914
    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Han Lin, Yu-Min Lin, Tao-Chih Chang
  • Patent number: 10672677
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 2, 2020
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, WIN-HOUSE ELECTRONIC CO., LTD.
    Inventors: Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin, Chih-Ming Tzeng, Hsiao-Ming Chang, Chih-Ming Shen
  • Publication number: 20180261519
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co., Ltd.
    Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
  • Publication number: 20170084521
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
    Type: Application
    Filed: May 4, 2016
    Publication date: March 23, 2017
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co.,Ltd.
    Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
  • Publication number: 20120282400
    Abstract: A method for making a cemented tungsten carbide-based material includes subjecting a cemented tungsten carbide substrate film to chromization so as to form the cemented tungsten carbide substrate with a chromized layer that contains a tungsten carbide and a chromium carbide and forming a diamond film on the chromized layer.
    Type: Application
    Filed: July 18, 2012
    Publication date: November 8, 2012
    Applicant: National Taiwan Ocean University
    Inventors: Chau-Chang Chou, Jyh-Wei Lee, Yen-Yi Chen, Hsin-Han Lin
  • Publication number: 20100104860
    Abstract: A cemented tungsten carbide-based material includes: a cemented tungsten carbide substrate having a chromized layer that contains a tungsten carbide and a chromium carbide; and a diamond film formed on said chromized layer. A method for making the cemented tungsten carbide-based material involves subjecting a cemented tungsten carbide substrate to chromization so as to form the cemented tungsten carbide substrate with a chromized layer that contains a tungsten carbide and a chromium carbide; and forming a diamond film on the chromized layer.
    Type: Application
    Filed: April 27, 2009
    Publication date: April 29, 2010
    Applicant: NATIONAL TAIWAN OCEAN UNIVERSITY
    Inventors: Chau-Chang Chou, Jyh-Wei Lee, Yen-Yi Chen, Hsin-Han Lin
  • Patent number: D976852
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin