Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, depositing a dielectric layer on the S/D region, forming a contact structure on the S/D region through the dielectric layer, removing a portion of the dielectric layer to expose sidewalls of the contact structure, forming a barrier layer on the dielectric layer and to cover the exposed sidewalls of the contact structure, and forming a via structure on the contact structure through the barrier layer. The formation of the barrier layer includes depositing an insulating layer with a dielectric constant and a material density higher than a dielectric constant and a material density of the dielectric layer.

Abstract: A memory device includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element, and a dielectric layer. The dielectric layer surrounds the bottom electrode, the resistance switching element, and the top electrode. The resistance switching element has a first portion between the top electrode and the dielectric layer.

Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.

Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.

Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.

Abstract: A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element.

Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

Abstract: A method for performing read acceleration, an associated data storage device and controller thereof are provided, where the method is applicable to the data storage device and the controller. The method includes: receiving a write command from a host device, and performing programming on a non-volatile (NV) memory element within a plurality of NV memory elements according to the write command; recording operation command-related information corresponding to the write command; when a read command having high priority exists in a queue corresponding to the NV memory element, suspending performing programming on the NV memory element; executing the read command; and after executing the read command, continuing performing programming on the NV memory element at least according to the operation command-related information.

Abstract: A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element.

Abstract: A method for performing programming management, associated memory device and a controller thereof are provided. The memory device may include a non-volatile (NV) memory, and the NV memory may include a plurality of NV memory elements. The method may include: before programming a target NV memory element of the plurality of NV memory elements, checking whether another NV memory element of the plurality of NV memory elements is in a busy state or in a non-busy state; and when the other NV memory element enters the non-busy state, programming the target NV memory element.

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.

Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.

Abstract: A method for performing read acceleration, an associated data storage device and controller thereof are provided, where the method is applicable to the data storage device and the controller. The method includes: receiving a write command from a host device, and performing programming on a non-volatile (NV) memory element within a plurality of NV memory elements according to the write command; recording operation command-related information corresponding to the write command; when a read command having high priority exists in a queue corresponding to the NV memory element, suspending performing programming on the NV memory element; executing the read command; and after executing the read command, continuing performing programming on the NV memory element at least according to the operation command-related information.