Patents by Inventor Hsin-Hua Lin
Hsin-Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072115Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: February 13, 2023Publication date: February 29, 2024Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
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Patent number: 11656222Abstract: A sensor using ultrasound to detect presence and nature of analyte includes an ultrasonic element and a receptor thereon. The ultrasonic element includes a first electrode, a second electrode facing and spaced apart from the first electrode, an insulating layer between the first electrode and the second electrode, and a vibrating film between the insulating layer and the first electrode. The vibrating film carries the first electrode. A cavity is formed between the vibrating film and the insulating layer. The receptor is on a side of the first electrode away from the second electrode. The receptor can combine with a target substance in a test analyte. When the first electrode and the second electrode are applied with different voltages, certain ultrasound frequencies are generated as the vibrating film vibrates, and the presence and weight of different target substances are indicated by the changes in resonance.Type: GrantFiled: March 30, 2020Date of Patent: May 23, 2023Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Hsin-Hua Lin, Wei-Chih Chang, Po-Li Shih, Chao-Chun Yang, I-Min Lu
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Patent number: 11289518Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.Type: GrantFiled: April 24, 2019Date of Patent: March 29, 2022Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin
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Publication number: 20210109092Abstract: A sensor using ultrasound to detect presence and nature of analyte includes an ultrasonic element and a receptor thereon. The ultrasonic element includes a first electrode, a second electrode facing and spaced apart from the first electrode, an insulating layer between the first electrode and the second electrode, and a vibrating film between the insulating layer and the first electrode. The vibrating film carries the first electrode. A cavity is formed between the vibrating film and the insulating layer. The receptor is on a side of the first electrode away from the second electrode. The receptor can combine with a target substance in a test analyte. When the first electrode and the second electrode are applied with different voltages, certain ultrasound frequencies are generated as the vibrating film vibrates, and the presence and weight of different target substances are indicated by the changes in resonance.Type: ApplicationFiled: March 30, 2020Publication date: April 15, 2021Inventors: HSIN-HUA LIN, WEI-CHIH CHANG, PO-LI SHIH, CHAO-CHUN YANG, I-MIN LU
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Patent number: 10978498Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.Type: GrantFiled: November 21, 2018Date of Patent: April 13, 2021Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Hsin-Hua Lin, Yi-Chun Kao
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Patent number: 10937881Abstract: A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.Type: GrantFiled: December 26, 2019Date of Patent: March 2, 2021Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Wei-Chih Chang, Hsin-Hua Lin, Po-Li Shih
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Patent number: 10727309Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).Type: GrantFiled: December 7, 2016Date of Patent: July 28, 2020Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
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Publication number: 20200209187Abstract: A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.Type: ApplicationFiled: December 26, 2019Publication date: July 2, 2020Inventors: WEI-CHIH CHANG, HSIN-HUA LIN, PO-LI SHIH
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Patent number: 10672880Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.Type: GrantFiled: December 13, 2016Date of Patent: June 2, 2020Assignees: HONG FU JIN PRECISION INDUSTRY (SheZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
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Patent number: 10504927Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).Type: GrantFiled: December 10, 2016Date of Patent: December 10, 2019Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
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Publication number: 20190252418Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: YI-CHUN KAO, HSIN-HUA LIN
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Patent number: 10347695Abstract: A display panel composed of red, green, blue, and white subpixels which avoids imaging artifacts is provided. The display panel defines a plurality of pixel units. Each pixel unit includes a complete red sub-pixel, a complete green sub-pixel, and a half-sized blue sub-pixel, and a half-sized white sub-pixel.Type: GrantFiled: March 13, 2018Date of Patent: July 9, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Wei-Chih Chang, Chung-Wen Lai, Hsin-Hua Lin, Kuo-Sheng Lee, Kuan-Hsien Jiang
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Patent number: 10319752Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.Type: GrantFiled: August 31, 2016Date of Patent: June 11, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yi-Chun Kao, Hsin-Hua Lin
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Patent number: 10276606Abstract: A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.Type: GrantFiled: August 18, 2017Date of Patent: April 30, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Hsin-Hua Lin, Yi-Chun Kao
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Publication number: 20190109160Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.Type: ApplicationFiled: November 21, 2018Publication date: April 11, 2019Inventors: HSIN-HUA LIN, YI-CHUN KAO
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Patent number: 10192897Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.Type: GrantFiled: August 31, 2016Date of Patent: January 29, 2019Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Hsin-Hua Lin, Yi-Chun Kao
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Publication number: 20190027571Abstract: A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.Type: ApplicationFiled: December 10, 2016Publication date: January 24, 2019Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: HSIN-HUA LIN, PO-LI SHIH, YI-CHUN KAO, CHANG-CHUN WAN, WEI-CHIH CHANG, I-WEI WU
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Publication number: 20190027505Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).Type: ApplicationFiled: December 10, 2016Publication date: January 24, 2019Applicants: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Yi-Chun KAO, Hsin-Hua LIN, Po-Li SHIH, Wei-Chih CHANG, Imin LU, Iwei WU
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Publication number: 20190027506Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.Type: ApplicationFiled: December 13, 2016Publication date: January 24, 2019Inventors: PO-LI SHIH, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, WEI-CHIH CHANG, I-MIN LU
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Publication number: 20190019870Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).Type: ApplicationFiled: December 7, 2016Publication date: January 17, 2019Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU