Abstract: Quick-release device carriers for computer chassis are described. In some embodiments, a carrier configured to couple and to decouple a device into or from a chassis may include: a front panel having a proximal edge, a distal edge opposite the proximal edge, and a handle nearest the proximal edge, where the proximal edge includes at least one protrusion; and a bracket slideable into the chassis, where the bracket includes a lateral portion and a rear portion, where the distal edge is coupled to the lateral portion via a hinge, where the rear portion includes an opening configured to accommodate an electronic connector between the device and the chassis, where the at least one protrusion is configured to latch onto at least one corresponding groove of a fixed portion of the chassis when the carrier is in a closed position, and where the fixed portion is parallel to the lateral portion.

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract: A key lock module for securing a chassis for use with an information handling system to a rack. The key lock module includes a bracket and a rotatable lock housed in the bracket. The rotatable lock includes a locking arm configured to rotate between a locked position and an unlocked position. The key lock module also includes a bracket hook having a first end and a second end. The first end is coupled to the bracket such that the bracket hook may be depressed when the rotatable lock is in the unlocked position. The second end is positioned to interface with the locking arm when the rotatable lock is in the locked position such that the bracket hook may not be depressed. The bracket hook also is configured to engage with a rack to prevent a chassis associated with the key lock module from being removed from the rack when the bracket hook is not depressed.

Abstract: A chip package is provided. The chip package includes a first substrate including a sensing region or device region. The chip package also includes a second substrate. The first substrate is mounted on the second substrate and is electrically connected to the second substrate. The ratio of the thickness of the first substrate to the thickness of the second substrate is in a range from 2 to 8.

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

Abstract: Quick-release device carriers for computer chassis are described. In some embodiments, a carrier configured to couple and to decouple a device into or from a chassis may include: a front panel having a proximal edge, a distal edge opposite the proximal edge, and a handle nearest the proximal edge, where the proximal edge includes at least one protrusion; and a bracket slideable into the chassis, where the bracket includes a lateral portion and a rear portion, where the distal edge is coupled to the lateral portion via a hinge, where the rear portion includes an opening configured to accommodate an electronic connector between the device and the chassis, where the at least one protrusion is configured to latch onto at least one corresponding groove of a fixed portion of the chassis when the carrier is in a closed position, and where the fixed portion is parallel to the lateral portion.

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad. The daughterboard includes at least one second signal pad electronically connected to the at least one first signal pad for electronically connecting the daughterboard to the motherboard.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: One embodiment of the present invention discloses a drying agent having the formula: [Mg2(BTEC)(H2O)m].nH2O, where m denotes zero or positive integer from 1 to 10, and n denotes zero or positive integer from 1 to 6. Another embodiment of the present invention provides a method for forming a drying agent.

Abstract: A method for controlling impedance of a multi-layer PCB includes establishing a geometric model using simulation software according to a structure of the multi-layer PCB. A first variable (S) and a second variable (W) are respectively defined in the simulation software. The variable S is set equal to a first desired value. An impedance (R) of the transmission line is set equal to a second desired value. The variable W is set to a value according to a relationship between R, S, and W.

Abstract: One embodiment of the present invention discloses a drying agent having the formula: [Mg2(BTEC)(H2O)m].nH2O, where m denotes zero or positive integer from 1 to 10, and n denotes zero or positive integer from 1 to 6. Another embodiment of the present invention provides a method for forming a drying agent.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.

Abstract: One embodiment of the present invention discloses a drying agent having the formula: [Mg2(BTEC)(H2O)m].nH2O, where m denotes zero or positive integer from 1 to 10, and n denotes zero or positive integer from 1 to 6. Another embodiment of the present invention provides a method for forming a drying agent.

Abstract: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.

Abstract: A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias.

Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.