Abstract: A frame module is provided, which is adapted to connect to an object unit. The frame module includes a module housing, a latch, and a cover. The object unit is connected to the module housing. The latch is connected to the module housing, which is adapted to be moved between the first latch position and the second latch position. When the latch is in the first latch position, the latch is connected to the object unit to restrict the object unit. When the latch is in the second latch position, the latch is separated from the object unit. The cover pivots on the module housing, which is adapted to be rotated between the first cover orientation and the second cover orientation. When the cover is in the first cover orientation, the cover presses the latch and keeps the latch in the first latch position.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

Abstract: An image inspection method includes capturing a target object image, which the target object image comprises a plurality of graphical features; choosing a block image comprising a specific graphical feature of the plurality of graphical features from the target object image; capturing all the graphical features of the block image to obtain a region of interest (ROI); executing a filtering process or a recovering process on the ROI to obtain a pre-processed region; and inspecting, according to the pre-processed region, the target object image to determine whether the target object image has defects.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

Abstract: A foldable display device, including a display panel, a pad portion, and a driving element, is provided. The display panel has a display region and a peripheral region connected to at least one side of the display region. The pad portion is disposed in the peripheral region. The driving element is electrically connected to the pad portion. A first display region folding line, extending along a first direction, is provided in the display region to divide the display region into a first sub-display region and a second sub-display region. A first peripheral region folding line and a second peripheral region folding line, extending along a second direction, are parallelly disposed in the peripheral region. A first notch is disposed at a position in the peripheral region. Along the first direction, the first notch has a first folding interval. Along the second direction, the first notch has a second folding interval.

Abstract: A multi-chip packaging structure employing millimeter wave includes a substrate material, a first and a second substrate board and an adhesive layer. The substrate material has a first metal pad. The first substrate board has a first and a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are layer-by-layer stacked and electrically connected. The first and second metal pads are electrically connected via at least one metal lead. The adhesive layer is disposed between the substrate material and the first substrate board. The second substrate board has a third and a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are layer-by-layer stacked and electrically connected. The electro-conductive boss blocks are respectively electrically connected with the second and third metal pads. Chips and antennas are integrated to integrate signal height and avoid interference and minify the volume.

Abstract: A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

Abstract: A flexible display including a buffer layer, a plurality of pixel structures, a plurality of first pads, a plurality of first conductive through holes, a flexible circuit board and an adhesive layer is provided. The pixel structures are disposed on a first surface of the buffer layer. The first pads are disposed on a second surface of the buffer layer. The first conductive through holes are embedded in the buffer layer. The first pads are respectively electrically connected to the pixel structures through the first conductive through holes. The adhesive layer is disposed between the second surface of the buffer layer and the flexible circuit board. An orthogonal projection of the adhesive layer on the buffer layer overlaps an orthogonal projection of the pixel structures on the buffer layer. The first pads are electrically connected to first signal lines of the flexible circuit board.

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Abstract: The disclosure provides a display panel including first pixel structures, second pixel structures, first signal lines, second signal lines, a first driving circuit, and a second driving circuit. The first signal lines and the first pixel structures are disposed in a first display area and electrically connected. The second signal lines and the second pixel structures are disposed in a second display area and electrically connected. The first display area and the second display area are arranged in a first direction. The first signal lines and the second signal lines are arranged in a second direction. The first direction and the second direction are perpendicular. The first signal lines and the second signal lines are structurally separated. The first drive circuit is electrically connected to the first signal lines. The second driving circuit is electrically independent from the first driving circuit and electrically connected to the second signal lines.

Abstract: A high-voltage device includes a substrate, at least a first isolation in the substrate, a first well region, a frame-like gate structure over the first well region and covering a portion of the first isolation, a drain region in the first well region and separated from the frame-like gate structure by the first isolation, and a source region separated from the drain region by the first isolation and the frame-like gate structure. The first well region, the drain region and the source region include a first conductivity type, and the substrate includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: A mobile device for detecting an oral pathology includes a casing, a probing unit, and a processor. The probing unit includes a fiber bundle set and a contact part configured to contact a gum portion of a tooth of an examinate. The fiber bundle set includes a light source fiber bundle and a light-receiving fiber bundle. The light source fiber bundle has a light-exiting end within the contact part, and can project a probing light onto the gum portion. The light-receiving fiber bundle has a light-receiving end within the contact part. The light-receiving fiber bundle can receive diffuse reflection lights generated after the probing light is diffuse reflected by the gum portion. The processor is in signal connection with the light-receiving fiber bundle, and can receive the diffuse reflection lights, to build an optical spectrum, and to determine a state of the gum portion according to the optical spectrum.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: A display device is provided. The display device includes a light-emitting unit. The light-emitting unit includes a light-emitting part, wherein a light extraction structure is disposed on a first surface of the light-emitting part. The light-emitting unit also includes a connective part disposed on a second surface opposite to the first surface of the light-emitting part. The light-emitting unit further includes a protective part surrounding the light-emitting part and the connective part. In addition, the display device includes a substrate having a plurality of active elements and at least one bonding pad, wherein the bonding pad is electrically connected to the corresponding connective part of the light-emitting unit. The roughness of the light extraction structure is greater than or equal to 0.2 ?m and less than or equal to 5 ?m.

Abstract: An apparatus is disclosed for improving zero voltage switching (“ZVS”) of a converter circuit such as an active clamp flyback converter. The apparatus includes a first timing circuit acting as the TD(L-H) optimizer, which uses the zero-crossing of the auxiliary winding voltage directly to adaptively vary the dead time. A second timing circuit acting as the TD(H-L) optimizer adaptively varies the dead time with a simple piece-wide linear function as an approximation of the complex optimal equation. A third timing circuit acting as the TDM optimizer contains a charge-pump circuit that adaptively adjusts the ON time of the clamp switch based on the zero-voltage detection of switching node voltage and feed-forwards the input voltage signal to enhance tuning speed so that the correct amount of negative magnetizing current is generated to improve zero voltage switching.

Abstract: Optoelectronic retinal prostheses transduce light into electrical current for neural stimulation. A novel optoelectronic pixel architecture is presented comprising a vertically integrated photo junction field-effect-transistor (Photo-JFET) and neural stimulating electrode. Experimental measurements demonstrate that optically addressed Photo-JFET pixels utilize phototransistive gain to produce a broad range of neural stimulation current and can effectively stimulate retinal neurons in vitro. The compact nature of the Photo-JFET pixel can enable high resolution retinal prostheses with a theoretical visual acuity ˜20/60 to help restore vision in patients with degenerative retinal diseases.

Abstract: the present invention provides a millimeter-wave up/down converter, with an internal signal source therein capable of manual coarse tuning and fine tuning, used for receiving and converting a low frequency/high frequency signal into a high frequency/low frequency signal to be used by a device in a user terminal, and comprises a micro-controller module, an adjusting switch, and a frequency-converter module. The micro-controller module is provided therein with a frequency control signal with a frequency within a frequency range. The adjusting switch is connected to the micro-controller module for adjusting the frequency control signal; thereby the adjusted frequency control signal is outputted from the micro-controller module.