Patents by Inventor Hsin-Neng Tai
Hsin-Neng Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9583527Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a floating diffusion disposed in the semiconductor material adjacent to a photodiode in the plurality of photodiodes. A transfer gate is disposed to transfer image charge generated in the photodiode into the floating diffusion. A first electrical contact with a first cross sectional area is coupled to the transfer gate. A second electrical contact with a second cross sectional area is coupled to the floating diffusion, and the second cross sectional area is greater than the first cross sectional area. The image sensor also includes pixel transistor region disposed in the semiconductor material including a first electrical connection to the semiconductor material. A third electrical contact with a third cross sectional area is coupled to the first electrical connection to the semiconductor material, and the third cross sectional area is greater than the first cross sectional area.Type: GrantFiled: January 28, 2016Date of Patent: February 28, 2017Assignee: OmniVision Technologies, Inc.Inventors: Kevin Ka Kei Leung, Hsin-Neng Tai, Hung-Ming Weng
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Patent number: 9385192Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: GrantFiled: July 27, 2015Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
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Patent number: 9349814Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: GrantFiled: June 4, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
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Patent number: 9343499Abstract: An integrated circuit system includes a first device and second device wafer. A wafer bonding region is disposed at an interface of a front side of a first dielectric layer of the first device wafer and a front side of a second dielectric layer of the second device wafer such that wafer bonding region bonds the first device wafer to the second device wafer. The wafer bonding region includes dielectric material having a higher silicon concentration than a dielectric material of the first and second dielectric layers of the first and second device wafers. A conductive path couples a first conductor of the first device wafer to a second conductor of the second device wafer. The conductive path is formed in a cavity etched through the wafer bonding region between the first conductor and the second conductor.Type: GrantFiled: April 23, 2015Date of Patent: May 17, 2016Assignee: OmniVision Technologies, Inc.Inventors: Hsin-Neng Tai, Hung-Ming Weng, Michael Chen, Chih-Huei Wu
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Patent number: 9257516Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.Type: GrantFiled: October 3, 2014Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Tsung-Liang Chen, Hsin-Neng Tai, Huey-Ming Wang
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Publication number: 20150333121Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
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Publication number: 20150270364Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: ApplicationFiled: June 4, 2015Publication date: September 24, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
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Patent number: 9123771Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: GrantFiled: February 13, 2013Date of Patent: September 1, 2015Assignee: GlobalFoundries Inc.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
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Patent number: 9093560Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: GrantFiled: September 20, 2013Date of Patent: July 28, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
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Publication number: 20150084131Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
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Publication number: 20150087134Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate iType: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Tsung-Liang CHEN, Hsin-Neng TAI, Puneet KHANNA, Zhenyu HU, Huey-Ming WANG
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Publication number: 20150048446Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.Type: ApplicationFiled: October 3, 2014Publication date: February 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Tsung-Liang CHEN, Hsin-Neng TAI, Huey-Ming WANG
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Patent number: 8927356Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.Type: GrantFiled: June 17, 2013Date of Patent: January 6, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Tsung-Liang Chen, Hsin-Neng Tai, Huey-Ming Wang, Puneet Khanna
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Publication number: 20140370697Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.Type: ApplicationFiled: June 17, 2013Publication date: December 18, 2014Inventors: Tsung-Liang Chen, Hsin-Neng Tai, Huey-Ming Wang, Puneet Khanna
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Publication number: 20140339642Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.Type: ApplicationFiled: May 17, 2013Publication date: November 20, 2014Inventors: Tsung-Liang CHEN, Hsin-Neng TAI, Huey-Ming WANG
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Patent number: 8877580Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.Type: GrantFiled: May 17, 2013Date of Patent: November 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Tsung-Liang Chen, Hsin-Neng Tai, Huey-Ming Wang
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Publication number: 20140227858Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim