REDUCTION OF OXIDE RECESSES FOR GATE HEIGHT CONTROL
An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.
1. Technical Field
The present invention generally relates to semiconductor devices and fabrication of the semiconductor devices. More particularly, the present invention relates to controlling gate height by reducing oxide recess and achieving gate height uniformity.
2. Background Information
Gate-first and Gate-last approaches have been two principle approaches for forming semiconductor device gate structures.
In a gate-first fabrication approach, a metal gate is provided over a gate dielectric, and then patterned and etched to form one or more gate structures. After forming the gate structures, source and drain features of the semiconductor devices are provided. In the gate-last approach, a sacrificial(or dummy) gate material is provided, patterned and etched to define one or more sacrificial gates. The one or more sacrificial gates are subsequently replaced with corresponding replacement metal gates, such as, for example, amorphous silicon (a-Si) or polycrystalline silicon, holds the position for the subsequent metal gate to be formed. For instance, an amorphous (a-Si) or polysilicon sacrificial gate material may be patterned and used during initial processing until high-temperature annealing to activate the source and drain features has been completed. Subsequently, the a-Si or polysilicon may be removed and replaced with the final metal gate.
During the fabrication process, a variety of gap fill materials such as, a flowable dielectric material (e.g. flowable oxide) are typically employed in the etched opening in the insulating layer between the adjacent gates, which would later be replaced by contact metal, during the subsequent fabrication processing. However, the quality of the gap fill may typically be poor and may be vulnerable to subsequent wet/dry etch processing. For example, when fabricating replacement metal gates with a tungsten metal gate, a sacrificial material is used between adjacent gate structures along with a fill material, such as a nitride over the entire structure. Subsequent chemical mechanical planarization of the tungsten and/or sacrificial nitride filler material may yield excessive recesses, particularly in the sacrificial material. Such recesses effect the resultant gate height.
Hence, there continues a need for a technique to control gate height, particularly due to oxidation recesses caused by processing of filler material.
SUMMARY OF THE INVENTIONThe shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of controlling gate oxide recess and gate height uniformity. The method includes providing an intermediate semiconductor structure in fabrication, the structure including a plurality of gate structures disposed over a substrate. The method further includes at least two of the gate structures separated by a sacrificial material between adjacent gate structures and creating substantially planar surface overlaying the plurality of gate structures and the sacrificial material to control sacrificial oxide recess and gate height.
The method may include selectively removing a portion of the sacrificial material between adjacent gate structures to form at least one or more openings within the sacrificial material, filling the at least one or more openings within the sacrificial material with a filler material, patterning a portion of the gate structures to form at least one or more gate openings within the gate structures and providing a plurality of gate caps over the at least one or more gate openings within the gate structures. The method may also include depositing the filler material within the at least one or more openings and over the gate structures and removing excess filler material over the at least one or more openings. And, the method may include depositing the gate caps within the one or more gate openings and extending over the adjacent filler material and removing excess gate cap over the one or more gate structures.
In accordance with another aspect, a semiconductor device is provided, including a substrate, a plurality of gate structures disposed over the substrate, at least two of the gate structures separated by a sacrificial material between adjacent gate structures. The structure may include a plurality of gate caps residing over and being in contact with the gate structures, and a filler material residing over and being in contact with the sacrificial material. The upper surface of the gate caps overlaying the gate structures is substantially planar with the upper surface of the filler material overlaying the sacrificial material so as to control sacrificial oxide recess and gate height.
The semiconductor device may include an intermediate structure which may further include a substrate, a plurality of gate structures, sacrificial material, gate caps and filler material.
These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures to designate the same or similar components.
Continuing with reference to
In one example, the gate dielectric layer 110 may be formed of a material such as silicon dioxide or a high-k dielectric material with a dielectric constant k greater than about 3.9 (e.g., k=3.9 for SiO2) and may be deposited by performing a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Examples of high-k dielectric materials that may be used in the gate dielectric layer 110 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.
One or more work-function layers 112 may be conformally deposited over the gate dielectric layer 110, for example, via a deposition process such as ALD, CVD or PVD. The work-function layer(s) 112 may include, for instance, one or more P-type metals or one or more N-type metals, depending on whether the gate structure is to include, for instance, a PFET or an NFET. The work-function layer(s) 112 may include an appropriate refractory metal nitride, for example, those from Groups IVa-VIa in the Periodic Table, including, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN), and the like. Although, the gate material 114 may include a metal, such as, for example, aluminum (Al), nickel (Ni), cobalt (Co), and titanium (Ti) and may be conformally deposited over the work function layer(s) 112 using processes, such as for instance, atomic layer deposition (ALD) or chemical vapor deposition (CVD), the gate material, used for the purposes of the present invention, may be tungsten. The gate material 114, in another example, may include polysilicon or polycrystalline silicon.
Continuing further with reference to
As will be subsequently explained, the present invention seeks to control recessing of the sacrificial oxide material and achieve uniformity of the gate structures by protecting the upper surface of sacrificial oxide material with a high aspect ratio oxide that is resistant to further fabrication processing techniques, such as, for example, chemical mechanical polishing and/or etch back processes. This may be accomplished by selectively removing a portion of the sacrificial oxide material and filling the opening within the sacrificial oxide material with a high aspect ratio filler material and removing the excess filler material over the openings. The invention further proceeds to selectively remove a portion of the gate structures and provide the etched portion of the gate structure with a gate cap material. Further fabrication processing such as, chemical mechanical polishing may be performed to achieve the gate height uniformity without affecting the adjacent sacrificial material, that is protected by the filler material.
As noted above and shown in
As illustrated in
The excess filler material 124 may then be selectively removed, as depicted in
As illustrated in
A gate cap material 138 may conformally be deposited in the one or more gate openings 132, 134 and 136, created within the gate structures and extended above the openings 126 filled with the filler material, as depicted in
As is shown in
Advantageously, as discussed above, the present invention controls recessing of the sacrificial material 116 by protecting the upper surface of the sacrificial oxide material with a high aspect ratio oxide 124 and minimizing/reducing the oxidation in the sacrificial material. The present invention further controls the gate height uniformity by creating a substantially planar surface between the gate structures protected by the gate caps and the sacrificial material protected by the high aspect ratio oxide.
While several aspects of the present invention have been described and depicted herein, alternative aspects may be effected by those skilled in the art to accomplish the same objectives. Accordingly, it is intended by the appended claims to cover all such alternative aspects as fall within the true spirit and scope of the invention.
Claims
1. A method comprising:
- facilitating fabricating an intermediate semiconductor structure, the facilitating fabricating comprising;
- providing a plurality of gate structures disposed over a substrate, at least two of the gate structures separated by a sacrificial material between adjacent gate structures; and
- creating substantially planar surface overlaying the plurality of gate structures and the sacrificial material to control sacrificial oxide recess and gate height.
2. The method of claim 1, wherein the facilitating comprises:
- selectively removing a portion of the sacrificial material between adjacent gate structures to form at least one or more openings within the sacrificial material;
- filling the at least one or more openings within the sacrificial material with a filler material;
- patterning a portion of the gate structures to form at least one or more gate openings within the gate structures; and
- providing a plurality of gate caps over the at least one or more gate openings within the gate structures.
3. The method of claim 2, wherein the filling comprises:
- depositing the filler material within the at least one or more openings and over the gate structures; and
- removing excess filler material over the at least one or more openings.
4. The method of claim 3, wherein removing the excess filler material comprises using the gate structures as an etch stop.
5. The method of claim 3, wherein the filler material further comprises a high aspect ratio oxide.
6. The method of claim 2, wherein the providing of gate structures comprises providing a gate dielectric over the substrate, at least one or more work function layers disposed over the gate dielectric and providing a gate material over the at least one or more work function layers.
7. The method of claim 6, wherein the gate dielectric comprises a high k-dielectric layer and the gate material comprises a metal gate.
8. The method of claim 2, wherein the patterning comprises selectively recessing at least a portion of the gate material within the gate structures to form one or more gate openings.
9. The method of claim 2, wherein the providing comprises:
- depositing the gate caps within the one or more gate openings and extending over adjacent filler material; and
- removing excess gate cap over the one or more gate structures.
10. The method of claim 9, wherein removing the excess gate cap comprises using the adjacent filler material as an etch stop.
11. The method of claim 10, wherein the gate cap comprises nitride cap.
12. A method comprising:
- providing a plurality of gate structures disposed over a substrate, at least two of the gate structures separated by a sacrificial material between adjacent gate structures;
- selectively removing a portion of the sacrificial material between the adjacent gate structures to form at least one or more openings within the sacrificial material;
- filling the at least one or more openings within the sacrificial material and over the gate structures with a filler material, wherein the filler material further comprises a high aspect ratio oxide;
- removing excess filler material over the at least one or more openings and using the gate structures as an etch stop;
- selectively removing a portion of the gate structures to form at least one or more gate openings within the gate structures;
- filling the at least one or more gate openings and over adjacent filler material with gate caps, wherein the gate caps further comprise nitride caps;
- removing excess gate cap over the at least one or more gate openings and using the adjacent filler material as an etch stop; and
- creating substantially planar surface overlaying the plurality of gate structures and the sacrificial material to control sacrificial oxide recess and gate height.
13. A semiconductor device comprising:
- intermediate structure comprising a substrate;
- a plurality of gate structures disposed over the substrate, at least two of the gate structures separated by a sacrificial material between adjacent gate structures;
- a plurality of gate caps residing over and being in contact with the gate structures and a filler material residing over and being in contact with the sacrificial material;
- wherein the upper surface of the gate caps overlaying the gate structures is substantially planar with the upper surface of the filler material overlaying the sacrificial material so as to control sacrificial oxide recess and gate height.
14. The semiconductor device of claim 13, wherein the filler material comprises a high aspect ratio oxide.
15. The semiconductor device of claim 13, wherein the gate structures comprises a gate dielectric over the substrate, at least one or more work function layers disposed over the gate dielectric and a gate material over the at least one or more work function layers.
16. The semiconductor device of claim 15, wherein the gate dielectric comprises a high k-dielectric layer and the gate material comprises a metal gate.
17. The semiconductor device of claim 13, wherein the gate cap comprises nitride cap.
Type: Application
Filed: May 17, 2013
Publication Date: Nov 20, 2014
Inventors: Tsung-Liang CHEN (Cohoes, NY), Hsin-Neng TAI (Clifton Park, NY), Huey-Ming WANG (Ballston Lake, NY)
Application Number: 13/896,807
International Classification: H01L 21/28 (20060101); H01L 29/423 (20060101); H01L 27/088 (20060101);