Patents by Inventor Hsin-Ping Chen
Hsin-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200403075Abstract: A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.Type: ApplicationFiled: August 29, 2020Publication date: December 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih WANG, Yu-Chieh LIAO, Tai-I YANG, Hsin-Ping CHEN
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Patent number: 10804143Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.Type: GrantFiled: July 1, 2019Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih-Wei Lu, Chung-Ju Lee
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Publication number: 20200299129Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a first dielectric layer formed over a substrate, and a first conductive layer formed in the first dielectric layer. The NEMS device structure includes a second dielectric layer formed over the first dielectric layer, and a first supporting electrode a second supporting electrode and a beam structure formed in the second dielectric layer. The beam structure is formed between the first supporting electrode and the second supporting electrode, and the beam structure has a T-shaped structure. The NEMS device structure includes a first through hole formed between the first supporting electrode and the beam structure, and a second through hole formed between the second supporting electrode and the beam structure.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Ping CHEN, Carlos H. DIAZ, Ken-Ichi GOTO, Shau-Lin SHUE, Tai-I YANG
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Patent number: 10763337Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.Type: GrantFiled: June 17, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
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Patent number: 10727113Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.Type: GrantFiled: December 5, 2019Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
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Patent number: 10676351Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer, wherein the beam structure includes a plurality of strip structures. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.Type: GrantFiled: June 15, 2018Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ping Chen, Carlos H. Diaz, Ken-Ichi Goto, Shau-Lin Shue, Tai-I Yang
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Publication number: 20200168458Abstract: A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.Type: ApplicationFiled: August 19, 2019Publication date: May 28, 2020Inventors: Yu-Chieh Liao, Cheng-Chi Chuang, Chia-Tien Wu, Tai-I Yang, Hsin-Ping Chen
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Patent number: 10622453Abstract: A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.Type: GrantFiled: April 22, 2019Date of Patent: April 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Yung-Chih Wang, Shin-Yi Yang, Chih-Wei Lu, Hsin-Ping Chen, Shau-Lin Shue
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Publication number: 20200111702Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
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Publication number: 20200105598Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.Type: ApplicationFiled: September 4, 2019Publication date: April 2, 2020Inventors: Tai-I Yang, Yu-Chieh Liao, Chia-Tien Wu, Hsin-Ping Chen, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20200006228Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: ApplicationFiled: April 10, 2019Publication date: January 2, 2020Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Patent number: 10504775Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.Type: GrantFiled: May 31, 2018Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
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Publication number: 20190371655Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
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Publication number: 20190326157Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Tai-I YANG, Wei-Chen CHU, Hsin-Ping CHEN, Chih-Wei LU, Chung-Ju LEE
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Publication number: 20190305100Abstract: A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih WANG, Yu-Chieh LIAO, Tai-I YANG, Hsin-Ping CHEN
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Publication number: 20190245054Abstract: A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Tai-I YANG, Yung-Chih WANG, Shin-Yi YANG, Chih-Wei LU, Hsin-Ping CHEN, Shau-Lin SHUE
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Patent number: 10340181Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.Type: GrantFiled: November 17, 2016Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih-Wei Lu, Chung-Ju Lee
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Patent number: 10325993Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.Type: GrantFiled: September 28, 2017Date of Patent: June 18, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih Wang, Yu-Chieh Liao, Tai-I Yang, Hsin-Ping Chen
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Patent number: 10269915Abstract: A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.Type: GrantFiled: June 7, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Yung-Chih Wang, Shin-Yi Yang, Chih-Wei Lu, Hsin-Ping Chen, Shau-Lin Shue
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Publication number: 20190097010Abstract: A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Chih WANG, Yu-Chieh LIAO, Tai-I YANG, Hsin-Ping CHEN