Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

Abstract: Embodiments generally relate to a chamber component to be used in plasma processing chambers for semiconductor or display processing. In one embodiment, a chamber component includes a textured surface having a surface roughness ranging from about 150 microinches to about 450 microinches and a coating layer disposed on the textured surface. The coating layer may be a silicon layer having a purity ranging from about 90 weight percent to about 99 weight percent, a thickness ranging from about 50 microns to about 500 microns, and an electrical resistivity ranging from about 1 E-3 ohm*m to about 1 E3 ohm*m. The coating layer provides strong adhesion for materials deposited in the plasma processing chamber, which reduces the materials peeling from the chamber component. The coating layer also enables oxygen plasma cleaning for further reducing materials deposited on the chamber component and provides the protection of the textured surface located therebelow.

Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: Embodiments generally relate to a chamber component to be used in plasma processing chambers for semiconductor or display processing. In one embodiment, a chamber component includes a textured surface having a surface roughness ranging from about 150 microinches to about 450 microinches and a coating layer disposed on the textured surface. The coating layer may be a silicon layer having a purity ranging from about 90 weight percent to about 99 weight percent, a thickness ranging from about 50 microns to about 500 microns, and an electrical resistivity ranging from about 1 E-3 ohm*m to about 1 E3 ohm*m. The coating layer provides strong adhesion for materials deposited in the plasma processing chamber, which reduces the materials peeling from the chamber component. The coating layer also enables oxygen plasma cleaning for further reducing materials deposited on the chamber component and provides the protection of the textured surface located therebelow.

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications, particularly for spin-orbit-torque magnetic random access memory (SOT MRAM) applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a magnetic tunnel junction (MTJ) pillar structure disposed on a substrate, and a gap surrounding the MTJ pillar structure. In yet another embodiment, a magnetic tunnel junction (MTJ) device structure includes a spacer layer surrounding a patterned reference layer and a tunneling barrier layer disposed on a patterned free layer, and a gap surrounding the patterned free layer.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: The present disclosure generally relates to spin-torque-transfer magnetoresistive random access memory (STT-MRAM) memory cells. In the magnetic tunnel junction (MTJ) of the STT-MRAM memory cell, a 1 nm thick barrier layer having a triclinic crystalline structure is doped with B, N, or C. By applying a positive voltage to the MTJ, the magnetic state of the free layer of the MTJ may be switched. By increasing the voltage applied to the MTJ, the MTJ may change to operate as a ReRAM memory cell, and the crystalline structure of the barrier layer may switch to monoclinic. Before reaching the breakdown voltage, a negative voltage may be applied to the MTJ to switch the crystalline structure of the barrier layer back to triclinic. Once the negative voltage is applied and the crystalline structure of the barrier layer is changed back to triclinic, the MTJ may function as a STT-MRAM cell once again.

Abstract: The embodiments of the present invention relate to a method for forming a magnetic read head having side by side sensors. The method includes depositing a pinned layer, a barrier layer and a free layer over a shield, and removing portions of the pinned layer, barrier layer and free layer to expose portions of the shield. A bias material is deposited over the exposed shield. An opening is formed in the free layer to expose the barrier layer, and an insulative material is deposited into the opening. The resulting side by side sensors each has its own free layer separated by the insulative nonmagnetic material. The side by side sensors share the pinned layer.