Abstract: The present invention is an image based oxygen saturation measuring device and method thereof. The method comprises steps of providing a plurality of red lights and a plurality of infrared lights arranged uniformly in an interlocked fashion and turned on alternatively; controlling the plurality of red lights and infrared lights to irradiate onto a selected skin area of a testee to have a red light turn-on period and an infrared light turn-on period; receiving a reflected version of the plurality of red lights and infrared lights from the selected skin area, respectively; and analyzing one reflected red light and one infrared light to acquire an oxygen saturation index for each of the coordination points. By means of the present invention, the measurement of oxygen saturation may be much exempted from effects brought from exterior interference and poor blood circulation, and may achieve a large measurement area in a single time.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: Disclosed are a method and system for eliminating yellow ring phenomenon occurring on the white light emitting diode (LED) based on a blue light chip exciting yellow phosphor powders and having a packaging surface enclosing thereon. Lightspot images are repeatedly acquired outside the white LED, and then each analyzed to see if the yellow ring still exists on a lightspot. If yes, a further atomization process is performed on the packaging surface of white LED, until the acquired and analyzed image shows no yellow ring exists. A lightspot-by-lightspot basis is used in the yellow ring elimination task. In the image analysis, a look up table may be provided in advanced or established at the same time simultaneously with the yellow ring elimination task. The atomization performed on the lightspot may also consider a width issue.

Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: The present invention provides an inspection method for inspecting defects of wafer surface. The method includes: encircling peripheral region of the wafer surface by a first light source set and a second light source set; using a control module to control the first light source set and the second light source set to irradiate the light alternately from different directions; using an image pick-up module to receive a scattered light image during each time when the first light source set or the second light source set irradiates the light on the wafer surface; and then using a process module to obtain an enhanced and clear defect image of wafer surface by processing each of the scattered light images.

Abstract: An inspection system and method for inspecting the surface defects of the specimen is provided. The inspection system includes a laser focus module, a microscope objective module, an image pick-up module, and a process module. The laser focus module configured to emit laser beam on the specimen by a predetermined angle relative to a surface of the specimen, and to generate scattered light and reflected light when the laser beam irradiates on the surface defects of the specimen. The process module can calculate the real size of the defects by using the intensity information obtained from the image pick-up module and the microscope objective module or using the diameter information obtained from the reflected light image while the reflected light projects on a screen.

Abstract: A method for fabricating an integrated circuit device is provided. In one embodiment, the method includes providing a substrate. A first photolithography process is performed to define a first pattern on the substrate. The first pattern includes a first trench segment. A second photolithography process is performed which defines a second pattern on the substrate. The second pattern includes a second trench segment. The second trench segment includes an overlap area with the first trench segment. The embodiment of the method further includes etching the substrate according the first and second patterns; the etching includes forming a via hole defined by the overlap area. The first trench segment, second trench segment, and via hole may be used to form a dual damascene interconnect structure.

Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.

Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

Abstract: Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: A method for fabricating an integrated circuit device is provided. In one embodiment, the method includes providing a substrate. A first photolithography process is performed to define a first pattern on the substrate. The first pattern includes a first trench segment. A second photolithography process is performed which defines a second pattern on the substrate. The second pattern includes a second trench segment. The second trench segment includes an overlap area with the first trench segment. The embodiment of the method further includes etching the substrate according the first and second patterns; the etching includes forming a via hole defined by the overlap area. The first trench segment, second trench segment, and via hole may be used to form a dual damascene interconnect structure.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

Abstract: A precious metal recovery device is revealed. A robot arm holds a cover of at least one loader for opening and moving the cover so as to put an object in or move an object out the loader. The loader is a pentagonal prism with an opening on one side thereof. The area of the opening is enlarged for convenience of loading objects containing precious metal. The loader is to receive the object containing the precious metal. By means of a conveying device, the loader is carried to an immersion device, at least one dissolver and at least one water cleaning device in sequence so as to recover precious metal from the objects containing precious metal. The precious metal recovery device recovers the precious metal continuously and automatically. Therefore, the speed of precious metal recovery is improved and the amount of precious metal recovered is increased.