Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: The present disclosure provides an improved method of parking a microelectromechanical system (MEMS) mirror in an array of MEMS mirrors to protect against single high voltage channel failures in a driver. Two separate voltages are applied to each MEMS mirror to move and park the mirror out of a camera sensor field of view in a servo system. For example, a first voltage may be applied in a positive X direction and a second voltage may be applied in a positive Y direction which will move the mirror in a diagonal direction. If one of the high voltage channels fail, the mirror will still be parked and outside of the camera sensor field of view. If a high voltage channel fails, the servo system can park a mirror affected by the failure in an opposite corner. Moreover, if 2-axis parking is not feasible, the mirror can use single-voltage parking.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, an active element, a driving circuit element, a first connection circuit, a second connection circuit and a conductive connector. The substrate has a first surface and a second surface opposite to the first surface. The active element is disposed on the first surface. The driving circuit element is disposed on the second surface and is overlapped with the active element. The first connection circuit is disposed on the first surface and is connected to the active element. The second connection circuit is disposed on the second surface and is connected to the driving circuit element. The conductive connector penetrates through the substrate and two ends of the conductive connector are electrically connected to the first connection circuit and the second connection circuit, respectively.

Abstract: The present invention provides a magnetic-control measurement system, comprises a reaction container and a programable magnetron measurement unit.

Abstract: The present disclosure provides an improved method of parking a microelectromechanical system (MEMS) mirror in an array of MEMS mirrors, wherein the method protects against single high voltage channel failures in a driver. Two separate voltages are applied to each MEMS mirror to move and park the mirror out of a camera sensor field of view in a servo system. For example, a first voltage may be applied in a positive X direction and a second voltage may be applied in a positive Y direction. This will then move the mirror in a diagonal direction. In the event one of the high voltage channels fail, the mirror will still be parked and outside of the camera sensor field of view. Using two voltages, every mirror will have 4 possible parking positions. In the event of a high voltage channel failure, the servo system can park a mirror affected by the failure in an opposite corner. Moreover, if 2-axis parking is not feasible, such as if both Y axes fail, the mirror can use single-voltage parking.

Abstract: A motor stator structure includes a core and plural hairpin wires. The core has slots, an insertion side, and an extension side. Each slot has an innermost layer, a second inner layer, a second outer layer and an outermost layer configured in a radial direction of the core. The hairpin leg protruding from the innermost layer extends for a first span distance, the hairpin leg protruding from the second inner layer extends for a second span distance, the hairpin leg protruding from the second outer layer extends for a third span distance, and the hairpin leg protruding from the outermost layer extends for a fourth span distance. The first span distance is different from the second span distance. The third span distance is different from the fourth span distance. The first and fourth span distances are substantially the same. The second and third span distances are substantially the same.

Abstract: A flexible electronic device has a display region and a package region surrounding the display region. The flexible electronic device includes a substrate, a first protection film, a first adhesive layer, a display medium layer, and a flexible auxiliary layer. The first protection film is disposed to be opposite to the substrate. The first adhesive layer is disposed between the substrate and the first protection film, and at least located within the package region. The display medium layer is disposed between the substrate and the first protection film, and located within the display region. The flexible auxiliary layer is disposed on a surface of the first protection film, and located within the package region, wherein the flexible auxiliary layer overlaps the first adhesive layer in a thickness direction.

Abstract: A motor stator structure includes a core and plural hairpin wires. The core has slots, an insertion side, and an extension side. Each slot has an innermost layer, a second inner layer, a second outer layer and an outermost layer configured in a radial direction of the core. The hairpin leg protruding from the innermost layer extends for a first span distance, the hairpin leg protruding from the second inner layer extends for a second span distance, the hairpin leg protruding from the second outer layer extends for a third span distance, and the hairpin leg protruding from the outermost layer extends for a fourth span distance. The first span distance is different from the second span distance. The third span distance is different from the fourth span distance. The first and fourth span distances are substantially the same. The second and third span distances are substantially the same.