Patents by Inventor Hsing Kuo TIEN
Hsing Kuo TIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387092Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11830834Abstract: A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.Type: GrantFiled: July 9, 2021Date of Patent: November 28, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsing Kuo Tien, Chih-Cheng Lee
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Patent number: 11721678Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: May 25, 2021Date of Patent: August 8, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Patent number: 11715694Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.Type: GrantFiled: July 12, 2021Date of Patent: August 1, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsing Kuo Tien, Chih Cheng Lee
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Publication number: 20230033515Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.Type: ApplicationFiled: October 10, 2022Publication date: February 2, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsing Kuo TIEN, Chih-Cheng LEE
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Publication number: 20230009219Abstract: A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsing Kuo TIEN, Chih-Cheng LEE
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Publication number: 20220418115Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.Type: ApplicationFiled: August 30, 2022Publication date: December 29, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
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Patent number: 11469186Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.Type: GrantFiled: July 24, 2020Date of Patent: October 11, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsing Kuo Tien, Chih-Cheng Lee
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Patent number: 11432406Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.Type: GrantFiled: September 18, 2020Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
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Publication number: 20220157745Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
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Patent number: 11335650Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.Type: GrantFiled: June 11, 2020Date of Patent: May 17, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
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Publication number: 20220095462Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
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Patent number: 11239184Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.Type: GrantFiled: June 11, 2020Date of Patent: February 1, 2022Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
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Publication number: 20220028801Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsing Kuo TIEN, Chih-Cheng LEE
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Publication number: 20210391284Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
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Publication number: 20210391283Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
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Publication number: 20210343648Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsing Kuo TIEN, Chih Cheng LEE
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Publication number: 20210280565Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11062996Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.Type: GrantFiled: July 31, 2019Date of Patent: July 13, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsing Kuo Tien, Chih Cheng Lee
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Patent number: 11018120Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: June 6, 2019Date of Patent: May 25, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien