Patents by Inventor Hsing Kuo TIEN

Hsing Kuo TIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210035912
    Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsing Kuo TIEN, Chih Cheng LEE
  • Publication number: 20200388600
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
  • Patent number: 10276507
    Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 30, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Hsing Kuo Tien
  • Publication number: 20180166370
    Abstract: A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Chai-Chi LIN, Chih-Cheng LEE, Hsing Kuo TIEN, Chih-Yung YANG
  • Patent number: 9997442
    Abstract: A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 12, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chai-Chi Lin, Chih-Cheng Lee, Hsing Kuo Tien, Chih-Yung Yang
  • Patent number: 9887167
    Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 6, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Hsing Kuo Tien, Li Chuan Tsai
  • Publication number: 20170301626
    Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Cheng LEE, Hsing Kuo TIEN
  • Patent number: 9721899
    Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: August 1, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Hsing Kuo Tien
  • Publication number: 20160064329
    Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.
    Type: Application
    Filed: June 5, 2015
    Publication date: March 3, 2016
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Cheng LEE, Hsing Kuo TIEN