Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: A semiconductor memory structure includes a memory cell, an encapsulation layer over a sidewall of the memory cell, and a nucleation layer between the sidewall of the memory cell and the encapsulation layer. The memory cell includes a top electrode, a bottom electrode and a data-storage element sandwiched between the bottom electrode and the top electrode. The nucleation layer includes metal oxide.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.

Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.

Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Abstract: A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.

Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.