Patents by Inventor Hsing-Lien Lin

Hsing-Lien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TOP-ELECTRODE BARRIER LAYER FOR RRAM
    Publication number: 20200411758
    Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: December 31, 2020
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Fa-Shen Jiang
  • Semiconductor device structure with multiple resistance variable layers
    Patent number: 10868247
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • MEMORY DEVICE STRUCTURE
    Publication number: 20200388756
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hai-Dang TRINH, Hsing-Lien LIN, Cheng-Yuan TSAI
  • Image Sensors with Organic Photodiodes and Methods for Forming the Same
    Publication number: 20200373357
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Method to enhance electrode adhesion stability
    Patent number: 10818544
    Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Organic photosensitive device with an electron-blocking and hole-transport layer
    Patent number: 10818857
    Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Switching layer scheme to enhance RRAM performance
    Patent number: 10811600
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Method of forming memory device with diffusion barrier and capping layer
    Patent number: 10804464
    Abstract: A structure and formation method of a semiconductor device structure is provided. The method includes forming a lower electrode layer over a semiconductor substrate and forming a data storage layer over the lower electrode layer. The method also includes forming an ion diffusion barrier layer over the data storage layer and forming a capping layer over the ion diffusion barrier layer. The ion diffusion barrier layer is a metal material doped with nitrogen, carbon, or a combination thereof. The capping layer is made of a metal material. The method further includes forming an upper electrode layer over the capping layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Cheng-Yuan Tsai
  • Semiconductor MEMS structure
    Patent number: 10787360
    Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a conductive mesa over the first substrate; forming a silicon containing layer over the mesa; and forming a cavity comprising a movable member proximal to the first substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • SEMICONDUCTOR DEVICE STRUCTURE WITH MULTIPLE RESISTANCE VARIABLE LAYERS
    Publication number: 20200274058
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • Image sensors with organic photodiodes and methods for forming the same
    Patent number: 10748967
    Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
  • FILM SCHEME TO IMPROVE PEELING IN CHALCOGENIDE BASED PCRAM
    Publication number: 20200161544
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell. The memory cell includes a bottom electrode overlying a substrate. A data storage structure overlies the bottom electrode. A top electrode overlies the data storage structure. Sidewalls of the top electrode and sidewall of the bottom electrode are aligned. Further, a getter layer abuts the bottom electrode.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Hai-Dang Trinh, Chin-Wei Liang, Hsing-Lien Lin, Fa-Shen Jiang
  • Semiconductor device structure with multiple resistance variable layers
    Patent number: 10658581
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first oxide layer over the lower electrode, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer. Oxygen ions are bonded more tightly in the second oxide layer than those in the first oxide layer, and oxygen ions are bonded more tightly in the second oxide layer than those in the third oxide layer. The semiconductor device structure further includes an upper electrode over the third oxide layer.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Chii-Ming Wu, Cheng-Yuan Tsai
  • Film scheme to improve peeling in chalcogenide based PCRAM
    Patent number: 10622555
    Abstract: A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The dielectric layer is disposed over a substrate. The bottom electrode overlies the dielectric layer. The via extends through the dielectric layer, from a bottom surface of the dielectric layer to a top surface of the dielectric layer. The phase change element overlies the bottom electrode. The getter metal layer is disposed between the dielectric layer and the PCE.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Chin-Wei Liang, Hsing-Lien Lin, Fa-Shen Jiang
  • RRAM STRUCTURE
    Publication number: 20200098985
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.
    Type: Application
    Filed: December 26, 2018
    Publication date: March 26, 2020
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • SWITCHING LAYER SCHEME TO ENHANCE RRAM PERFORMANCE
    Publication number: 20200052200
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20200052203
    Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode over the bottom electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the top electrode and the switching layer. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: HAI-DANG TRINH, FA-SHEN JIANG, HSING-LIEN LIN, CHII-MING WU
  • FILM SCHEME TO IMPROVE PEELING IN CHALCOGENIDE BASED PCRAM
    Publication number: 20200044148
    Abstract: A phase change memory (PCM) device including a PCM structure with a getter metal layer disposed between a phase change element (PCE) and a dielectric layer is provided. The PCM structure includes a dielectric layer, a bottom electrode, a via, a PCE, and a getter metal layer. The dielectric layer is disposed over a substrate. The bottom electrode overlies the dielectric layer. The via extends through the dielectric layer, from a bottom surface of the dielectric layer to a top surface of the dielectric layer. The phase change element overlies the bottom electrode. The getter metal layer is disposed between the dielectric layer and the PCE.
    Type: Application
    Filed: December 3, 2018
    Publication date: February 6, 2020
    Inventors: Hai-Dang Trinh, Chin-Wei Liang, Hsing-Lien Lin, Fa-Shen Jiang
  • THERMAL DISPERSION LAYER IN PROGRAMMABLE METALLIZATION CELL
    Publication number: 20200006649
    Abstract: Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 2, 2020
    Inventors: Fa-Shen Jiang, Hsing-Lien Lin
  • Switching layer scheme to enhance RRAM performance
    Patent number: 10505107
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a lower electrode over a conductive interconnect, and an upper electrode over the lower electrode. A data storage structure is disposed between the lower electrode and the upper electrode. The data storage structure includes a plurality of metal oxide layers having one or more metals from a first group of metals. A concentration of the one or more metals from the first group of metals changes as a distance from the lower electrode increases.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu