Patents by Inventor Hsing Liu

Hsing Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8427840
    Abstract: A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: April 23, 2013
    Assignee: Fortune Semiconductor Corporation
    Inventors: Kuo-Chiang Chen, Arthur Shaoyan Rong, Chen Hsing Liu, Yen-Yi Chen
  • Patent number: 8416657
    Abstract: A method for managing data from a host to an optical disc includes: storing data into a write data queue (WDQ) when the data of sequential write commands from the host are write-address-discontinuous; and transferring specific data from the WDQ to a write buffer when an available memory space in the WDQ is lower than a first threshold value or an available memory space in the write buffer exceeds a second threshold value.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: April 9, 2013
    Assignee: Mediatek Inc.
    Inventors: Tun-Hsing Liu, Tzu-Wei Kuo
  • Publication number: 20130075880
    Abstract: A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 28, 2013
    Applicant: FORTUNE SEMICONDUCTOR CORPORATION
    Inventors: KUO-CHIANG CHEN, ARTHUR SHAOYAN RONG, CHEN HSING LIU, YEN-YI CHEN
  • Publication number: 20130075882
    Abstract: A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 28, 2013
    Applicant: FORTUNE SEMICONDUCTOR CORPORATION
    Inventors: KUO-CHIANG CHEN, ARTHUR SHAOYAN RONG, CHEN HSING LIU, YEN-YI CHEN
  • Patent number: 8383508
    Abstract: The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a first opening that exposes a surface of the conductive region.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: February 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Hsing Liu, Chia-Hsiun Yu
  • Publication number: 20120276722
    Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate , each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.
    Type: Application
    Filed: July 6, 2011
    Publication date: November 1, 2012
    Inventors: Jen-Inn CHYI, Hsueh-Hsing Liu, Hsien Yu Lin
  • Patent number: 8237174
    Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: August 7, 2012
    Assignee: National Central University
    Inventors: Peng-Ren Chen, Hsueh-Hsing Liu, Jen-Inn Chyi
  • Patent number: 8217670
    Abstract: The invention provides a label-free sensor that includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and spaced away from the first electrode, and a semiconductor layer formed on the substrate and being in contact with the first electrode and the second electrode. The semiconductor layer has a plurality of probe groups bonded to the semiconductor layer by functionalization, for sensing a coupling-specific substance having bonding specificity with the probe groups. The semiconductor layer is bonded with the probe groups, and the detection of detected object is performed in an instant, quick, rapid, and sensitive manner by measuring variation in electric current, avoiding the use of fluorescent reading equipment for reading fluorescent signals.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 10, 2012
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Sheng-Fu Hong, Yu-Chiang Chao, Chien-Cheng Liu, Wen-Hsing Liu, Cheng-Chung Chang, Jan-Hao Li, Ming-Zhi Dai
  • Publication number: 20120172324
    Abstract: The present disclosure relates generally to a co-formulation or co-administration of acetaminophen with one or more chemicals that are metabolites or their derivatives in the methionine and glutathione biosynthesis pathways, for protection against acetaminophen-induced liver toxicity. The formulation may comprise acetaminophen and diet supplements such as S-methylmethionine (SMM). The present disclosure also encompasses methods of providing pain or fever relief with protection against acetaminophen-induced liver injury with the formulations described herein. Embodiments of the present disclosure also include co-formulation or co-administration of an agent and one or more other chemicals for reducing agent-induced liver toxicity via depletion of glutathione.
    Type: Application
    Filed: September 16, 2010
    Publication date: July 5, 2012
    Inventors: Hong-Hsing Liu, Gary Allen Peltz, Guochun Liao, Timothy Alan Garrow
  • Patent number: 8203916
    Abstract: A control unit accesses a memory. The memory includes a plurality of blocks. The control unit includes a batch buffer, a batch controller and a multiplexer. The batch buffer stores a batch which includes a designated block index. The batch controller fetches the designated block index from the batch buffer. The multiplexer selectively outputs a sequential block index or the designated block index as an active index according to a control signal. And a designated block of the memory is accessed according to the active index.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: June 19, 2012
    Assignee: Mediatek Inc.
    Inventors: Tun-Hsing Liu, Chih-Chuan Chen, Kun-Chieh Yang
  • Patent number: 8196059
    Abstract: A system with switch and on-screen display function includes a display device and a switch device. The display device includes a display panel and a display circuit. The display circuit is coupled with the display panel and is configured to control the display device. The display circuit includes an on-screen display generating circuit. The switch device is coupled with the display device and is configured to switch an access to one of at least two computers. The on-screen display generating circuit includes a signal receiving circuit, a processing circuit and a signal outputting circuit. The signal receiving circuit is configured to receive command signals from the switch device. The processing circuit generates first on-screen display menu signals for providing a first on-screen display menu in response to the received command signals. The signal outputting circuit of the on-screen display generating circuit provides the first on-screen display signals to the display panel.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: June 5, 2012
    Assignee: Aten International Co., Ltd.
    Inventors: Sun-Chung Chen, Chien-Hsing Liu, Wei-Min Huang
  • Publication number: 20120127671
    Abstract: A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: FORTUNE SEMICONDUCTOR CORPORATION
    Inventors: KUO-CHIANG CHEN, ARTHUR SHAOYAN RONG, CHEN HSING LIU, YEN-YI CHEN
  • Patent number: 8180938
    Abstract: A method for automatic learning of software keyboard input characteristics includes the following steps. (a) An input is received. (b) Whether the input is a normal key input is determined. (c) The input value of the input is stored when the input is determined to be the normal key input. (d) Step (a)-(c) are repeated until (N+1) input values are stored, wherein N is a positive integer. (e) When there are (N+1) inputs stored, the input characteristics of the first input in the (N+1) inputs are determined according to the first stored input value in the stored (N+1) input values. A computer program product using the method and a system for automatic learning of software keyboard input characteristics are also disclosed herein.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 15, 2012
    Assignee: HTC Corporation
    Inventor: Pei-Hsing Liu
  • Patent number: 8089842
    Abstract: A system and method of controlling data recording process of optical recording medium in a sequential writing are described. The control system comprises an information unit, a data-preparing unit and a recording controller. The information unit generates an information signal. The data-preparing unit prepares the data for recording. The data is then transformed into a writing signal according to the information signal. The recording controller controls the data-preparing unit to adjust the writing signal while acquiring the information signal during a sequential writing. Thus, the recording controller adjusts the writing signal according to the information signal. The data-preparing unit outputs the adjusted writing signal having desired recording area and undesired recording area and the adjusted writing signal is recorded on the optical recording medium during the sequential writing. The adjusted writing signal is outputted to OPU. The OPU performs a recording process of the optical recording medium.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: January 3, 2012
    Assignee: Mediatek Inc.
    Inventors: Tun-hsing Liu, Hong-ching Chen, Yu-wei Ling
  • Publication number: 20110272719
    Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Inventors: Peng-Ren Chen, Hsueh-Hsing Liu, Jen-Inn Chyi
  • Patent number: 8048542
    Abstract: A bis-phenanthroimidazolyl compound having a following formula is disclosed. Where A1 and A2 comprise identical or different aromatic rings, A3 comprises a polyaromatic hydrocarbon or at least two aromatic groups, and each carbon in A1 to A3 and phenanthrol groups is independently substituted or non-substituted. The bis-phenanthroimidazolyl compound exhibits relatively better thermal properties with higher glass-transition temperature and efficient blue emission. The bis-phenanthroimidazolyl compound may function as a host emitter or charge-transporter. An electroluminescent device is also disclosed.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: November 1, 2011
    Assignee: National Tsing Hua University
    Inventors: Chien-Hong Cheng, Charng-Hsing Liu, Fang-Iy Wu
  • Patent number: 8048786
    Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: November 1, 2011
    Assignee: National Central University
    Inventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu
  • Patent number: 7940019
    Abstract: A control module adapted to brush and brushless motors essentially applies a magnetic sensor to generate detecting signals in response to the status of the motor and deliver those signals to a control unit. The control unit further converts the signals into discrete diverting signals for driving the rotating direction, phase commands for controlling the motor phase, and a pulse width modulation (PWM) for adjusting the motor speed. A phase refining circuit thence receives those transformed signals and confirms merely a selected phase command attendant with the diverting and PWM signals for assisting a stable operation of the motor. Therefore, such control module not only applies to different types of motors but uses the separate transmissions of the signals responsible for designated instructions to attain facile controls and appropriate adjustments to the errors of the motor phase or motor velocity and efficiently decrease the occurrence of breaking the motor.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 10, 2011
    Assignee: STL Technology Co., Ltd.
    Inventors: Shing-Jung Wu, Kuei-Hsing Liu
  • Publication number: 20110045658
    Abstract: A method for fabricating a semi-polar nitride semiconductor is disclosed, comprising following steps: firstly, a (001) substrate tilted at 7 degrees and having a plurality of V-like grooves is provided, and tilted surfaces of the V-like groove are a (111) surface at 61.7 degrees and a ( 1 11) surface at 47.7 degrees; next, a surface of said substrate is cleaned by using a deoxidized solution, and then a buffer layer is formed on said substrate to cover said V-like grooves; then, said buffer layer is covered with an oxide layer except for said buffer layer formed on said (111) surface at 61.7 degrees; and finally, said semi-polar nitride semiconductor is formed on said buffer layer having (111) surface at 61.7 degrees to enhance the quality of said semi-polar nitride semiconductor.
    Type: Application
    Filed: December 17, 2009
    Publication date: February 24, 2011
    Inventors: Hsueh-hsing LIU, Jen-inn Chyi, Chin-chi Wu
  • Publication number: 20110036224
    Abstract: A cutting angle adjustment device for a circular saw machine includes: a base frame; a worktable rotatably mounted on the base frame; a fine-adjustment unit disposed on a frontward area of the base frame and having an arcuate rack segment; and an adjustment actuating unit having a pinion engageable with the rack segment, an actuating shaft rotatably and movably mounted on an arm of the worktable and coupled with the pinion such that, when the actuating shaft is moved from a normal position to a pressed position, the pinion-is brought into engagement with the rack segment to enable angular movement of the arm relative to the base frame for fine-adjustment of the cutting angle of the worktable, and a biasing member disposed to bias the actuating shaft to the normal position.
    Type: Application
    Filed: August 13, 2009
    Publication date: February 17, 2011
    Inventor: Chien-Hsing Liu