Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: In the present invention an EEPROM flash memory is operated using the I/O pins of an EPROM. A novel circuit is used that allows a plurality of voltages to be applied at different times to a single pin designated as CEB (chip enable bar) that permits reading and writing of the flash memory chip. The plurality of voltages can range from a positive voltage, to a ground voltage and to a negative voltage. When a positive voltage like Vdd is applied to the the CEB pin the chip is disabled and entered into a standby mode. When a ground voltage is applied to the CEB pin, the flash memory chip is enabled and a read operation can be performed. When a high negative voltage is applied to the CEB pin, the circuit of the present invention produces an internal high negative voltage to be used for a write operation.

Abstract: In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.

Abstract: A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.

Abstract: The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded.

Abstract: A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Abstract: Data stored in multi-level memory cells is rapidly read out with high resolution by generating and coupling a predetermined and preferably low number of large magnitude jump-like voltage changes to the control gates of the memory cells. The magnitude of the jumps can be a substantial fraction of the power supply level and will be many times the &Dgr;Vt levels associated with the memory cells, e.g., the control gate voltage changes in jump-steps from say 4 V to 6 V to 8 V. Use of a low number of jump-steps (e.g., two or three) reduces read out time by permitting read out of a plurality of Vt levels during a given control voltage magnitude. Further, use of large but different magnitude control gate voltages provides good read out resolution over the range of Vt values. Reference cells are provided to improve tracking, and DRAM-type sense amplifiers are provided to maintain high noise immunity.

Abstract: A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

Abstract: In the present invention an array for a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The device is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons into the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.

Abstract: Bias conditions for improving the efficiency of repairing, programming and erasing the threshold voltages of non-volatile memory devices. A positive voltage is applied to the source region of a non-volatile memory cell. The control gate of the memory cell is applied with another positive voltage higher the voltage at the source region. The difference between the two voltages is proportional to the desired final threshold voltage. The drain region can be applied with a positive voltage directly from the power supply of the memory device. A negative voltage is applied to the bulk of the memory device so that a large electric field across the control gate and the bulk can induce hot-electron injection. By selecting the proper voltage level at the control gate, the method can be used for the repair, program or erase operation of memory devices.

Abstract: In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

Abstract: In this invention a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The cell is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons in to the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.

Abstract: A two-phase high voltage generator circuit is electronically reconfigurable to output positive (V.sub.Pp) or negative (V.sub.Pn) high voltage, depending upon whether positive or negative mode operation is selected. The circuit includes a plurality of series-connected charge multiplier stages that each comprises a MOS transistor and a charging capacitor. Collectively the stages define an anode node and a cathode node. One of two non-overlapping phase signals is coupled to the free end of each charging capacitor such that adjacent charging capacitors are driven by different phases. First and second two-way multiplexers (MUX1, MUX2) control voltages presented to the anode and cathode nodes, to determine whether circuit operation is positive or negative mode. The MOS devices may be PMOS or NMOS, and preferably Vt-cancellation is provided for each charging stage. A precharge/discharge circuit preferably is coupled to each voltage node including the load capacitor.

Abstract: An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes.

Abstract: New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well.

Abstract: Charge pump circuits for stepping up high voltages for flash memory array are disclosed. A first circuit comprises a plurality of series-coupled charge pumps having pump capacitors connected to each pump stage. A first group of charge pumps of the pump circuit are AC coupled through pump capacitors to two non-overlapping pulse trains. To reduce the high voltage that a pump capacitor has to withstand, each pump capacitor after the first group is connected to an earlier pump stage instead of the non-overlapping pulse trains. Therefore, the charge pump circuit can output voltage higher than the breakdown voltage of the pump capacitors. A second circuit comprising a configurable charge pump circuit is also presented.

Abstract: A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file.

Abstract: A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.