Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A pixel array substrate, including a substrate, multiple conductors, a pixel driving circuit, a first pad, and a second pad, is provided. The substrate has a first surface, a second surface, and multiple through holes. The through holes extend from the first surface to the second surface. The conductors are respectively disposed in the through holes. The pixel driving circuit is disposed on the first surface of the substrate. The first pad and the second pad are disposed on the second surface of the substrate. The conductors include a first conductor, a second conductor, and a first dummy conductor. The first conductor is electrically connected to the pixel driving circuit and the first pad. The second conductor is electrically connected to the pixel driving circuit and the second pad. The first dummy conductor is overlapped with and electrically isolated from the pixel driving circuit.

Abstract: A pixel array substrate, including a substrate, multiple conductors, a pixel driving circuit, a first pad, and a second pad, is provided. The substrate has a first surface, a second surface, and multiple through holes. The through holes extend from the first surface to the second surface. The conductors are respectively disposed in the through holes. The pixel driving circuit is disposed on the first surface of the substrate. The first pad and the second pad are disposed on the second surface of the substrate. The conductors include a first conductor, a second conductor, and a first dummy conductor. The first conductor is electrically connected to the pixel driving circuit and the first pad. The second conductor is electrically connected to the pixel driving circuit and the second pad. The first dummy conductor is overlapped with and electrically isolated from the pixel driving circuit.

Abstract: A device substrate including a substrate, first fan-out lines, second fan-out lines, third fan-out lines, touch electrode lines, and active devices is provided. The substrate includes an active area and a peripheral area connected with the active area. The first fan-out lines, the second fan-out lines, and the third fan-out lines are disposed on the peripheral area. Each of the second fan-out lines is overlapped with one corresponding first fan-out line. The second fan-out lines and the first fan-out lines belong to different conductive layers. Each of the third fan-out lines is disposed between two corresponding first fan-out lines. The third fan-out lines and the first fan-out lines belong to the same conductive layer. The touch electrode lines are electrically connected with the third fan-out lines. The active devices are disposed on the active area and electrically connected with the first fan-out lines and the second fan-out lines.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: A pixel array substrate including a plurality of pixel units disposed on a substrate is provided. Each of the pixel units includes a scan line, a data line and an active element. The active element includes a semiconductor layer, a gate, a source electrode and a drain electrode. The semiconductor layer has a channel region, a source region, a drain region, a first connection region and a second connection region. The first connection region is connected between the channel region and the source region. The second connection region is connected between the channel region and the drain region. A normal projection of the first connection region on the substrate and a normal projection of the second connection region on the substrate are respectively located at two opposite sides of a normal projection of the data line on the substrate.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: A pixel array substrate including a plurality of pixel units disposed on a substrate is provided. Each of the pixel units includes a scan line, a data line and an active element. The active element includes a semiconductor layer, a gate, a source electrode and a drain electrode. The semiconductor layer has a channel region, a source region, a drain region, a first connection region and a second connection region. The first connection region is connected between the channel region and the source region. The second connection region is connected between the channel region and the drain region. A normal projection of the first connection region on the substrate and a normal projection of the second connection region on the substrate are respectively located at two opposite sides of a normal projection of the data line on the substrate.

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.

Abstract: A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.

Abstract: A light-emitting device and the fabrication method thereof. A substrate is provided. A plurality of active elements are formed on the substrate, defining a plurality of pixel areas. A color filter is formed on the pixel areas. The surface of the color filter is planarized to reduce roughness. An electrode is formed on the color filter. An light-emitting layer is formed on the electrode. A second electrode is formed on the light-emitting layer.

Abstract: A light-emitting device and the fabrication method thereof. A substrate is provided. A plurality of active elements are formed on the substrate, defining a plurality of pixel areas. A color filter is formed on the pixel areas. The surface of the color filter is planarized to reduce roughness. An electrode is formed on the color filter. An light-emitting layer is formed on the electrode. A second electrode is formed on the light-emitting layer.

Abstract: A light-emitting device and the fabrication method thereof. A substrate is provided. A plurality of active elements are formed on the substrate, defining a plurality of pixel areas. A color filter is formed on the pixel areas. The surface of the color filter is planarized to reduce roughness. An electrode is formed on the color filter. An light-emitting layer is formed on the electrode. A second electrode is formed on the light-emitting layer.

Abstract: Array substrates for electroluminescent (EL) devices and methods of forming the same are disclosed. The array substrates for electroluminescent (EL) devices include a substrate with at least one thin film transistor formed thereon, covered by a planarization layer. A first dielectric passivation layer with a contact hole therein covers parts of the planarization layer and exposes a source/drain electrode of the thin film transistor. A transparent electrode covers a portion of the first electric passivation layer and fills the contact hole, and is partly exposed by a patterned second dielectric passivation formed thereon. A plurality of spacers covers a portion of the second dielectric passivation layer to define an organic electroluminescent area with an exposed transparent electrode. An organic electroluminescent layer covers the exposed transparent electrode, and an electrode covers the organic electroluminescent layer.

Abstract: An active matrix organic light emitting display and a method of forming the same. The AM-OLED including a substrate with a plurality of thin film transistors serving as driver circuits, a dielectric layer formed conformally on the substrate and the thin film transistors, a first insulating layer formed on parts of the dielectric layer to define the exposed surface of the dielectric layer as a predetermined transparent electrode area, a transparent electrode formed conformally on the predetermined transparent electrode area, a second insulating layer formed on both sides of the transparent electrode to expose parts of surface of the transparent electrode, an organic electroluminescent layer formed on the transparent electrode, and a metal electrode formed on the organic electroluminescent layer. The insulating layer smoothes the transparent electrode surface enhancing the luminescent characteristics of the AM-OLED.

Abstract: A thin film transistor for use in an active matrix liquid crystal display includes a substrate, a source and a drain regions, and at least a gate electrode. The substrate includes therein a plurality of intrinsic regions, at least one first doped region and two second doped regions. The first doped region is disposed between the plurality of intrinsic regions. The plurality of intrinsic regions are linked together to form a connection structure via the first doped region, and the two second doped regions are disposed at both ends of the connection structure, respectively. The source and the drain regions are coupled to the two second doped regions disposed at both ends of the connection structure, respectively. The gate electrode is disposed over the plurality of intrinsic regions, such that the periphery of each of the plurality of intrinsic regions and the periphery of a corresponding gate electrode are substantially aligned with each other.