Patents by Inventor Hsiu Han
Hsiu Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210151447Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.Type: ApplicationFiled: October 1, 2020Publication date: May 20, 2021Inventors: Che-Fu CHUANG, Jian-Ting CHEN, Yu-Kai LIAO, Hsiu-Han LIAO
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Patent number: 10971508Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.Type: GrantFiled: April 23, 2019Date of Patent: April 6, 2021Assignee: Winbond Electronics Corp.Inventors: Yao-Ting Tsai, Che-Fu Chuang, Jung-Ho Chang, Hsiu-Han Liao
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Publication number: 20200343256Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Applicant: Winbond Electronics Corp.Inventors: Yao-Ting Tsai, Che-Fu Chuang, Jung-Ho Chang, Hsiu-Han Liao
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Publication number: 20200273871Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.Type: ApplicationFiled: September 12, 2019Publication date: August 27, 2020Applicant: Winbond Electronics Corp.Inventors: Jian-Ting Chen, Yao-Ting Tsai, Hsiu-Han Liao
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Patent number: 10699975Abstract: A semiconductor device having a conductive pad is provided, wherein the conductive pad includes a substrate, a dielectric layer, a plurality of vias, and a patterned conductive pad. The dielectric layer is overlying the substrate. The vias are disposed in the dielectric layer. The patterned conductive pad is disposed over the dielectric layer. The conductive pad includes, from a top view, at least three first conductive strips spaced apart from each other, arranged in different rows. The conductive strips in different rows are electrically and physically connected by a plurality of conductive strings. The conductive strings between different rows of the conductive strips are arranged in a staggered manner. The vias are disposed under the conductive strips.Type: GrantFiled: October 25, 2018Date of Patent: June 30, 2020Assignee: WINBOND ELECTRONICS CORP.Inventors: Lun-Lun Chen, Hsiu-Han Liao, Yao-Ting Tsai
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Patent number: 10615087Abstract: A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.Type: GrantFiled: October 9, 2018Date of Patent: April 7, 2020Assignee: WINBOND ELECTRONICS CORP.Inventors: Hsiu-Han Liao, Che-Fu Chuang
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Publication number: 20200035794Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.Type: ApplicationFiled: July 24, 2019Publication date: January 30, 2020Inventors: Jian-Ting CHEN, Yao-Ting TSAI, Jung-Ho CHANG, Hsiu-Han LIAO
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Publication number: 20190305110Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures formed on the substrate. The method also includes forming a spacer liner on the gate structures and the substrate. The method also includes forming a sacrificial layer between the gate structures and on the gate structures. The method also includes forming a plurality of dielectric plugs through the sacrificial layer above the gate structures. The method also includes removing the sacrificial layer to form a plurality of contact openings between the gate structures. The method also includes forming an etch resistant layer conformally covering the sidewall and the bottom of the contact openings. The method also includes forming a plurality of contact plugs in the contact openings.Type: ApplicationFiled: April 3, 2019Publication date: October 3, 2019Inventors: Sih-Han CHEN, Chien-Ting CHEN, Yao-Ting TSAI, Hsiu-Han LIAO
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Publication number: 20190221487Abstract: A semiconductor device having a conductive pad is provided, wherein the conductive pad includes a substrate, a dielectric layer, a plurality of vias, and a patterned conductive pad. The dielectric layer is overlying the substrate. The vias are disposed in the dielectric layer. The patterned conductive pad is disposed over the dielectric layer. The conductive pad includes, from a top view, at least three first conductive strips spaced apart from each other, arranged in different rows. The conductive strips in different rows are electrically and physically connected by a plurality of conductive strings. The conductive strings between different rows of the conductive strips are arranged in a staggered manner. The vias are disposed under the conductive strips.Type: ApplicationFiled: October 25, 2018Publication date: July 18, 2019Inventors: Lun-Lun CHEN, Hsiu-Han LIAO, Yao-Ting TSAI
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Publication number: 20190181063Abstract: A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.Type: ApplicationFiled: October 9, 2018Publication date: June 13, 2019Inventors: Hsiu-Han LIAO, Che-Fu CHUANG
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Patent number: 10147730Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.Type: GrantFiled: March 15, 2018Date of Patent: December 4, 2018Assignee: Winbond Electronics Corp.Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
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Publication number: 20180204846Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.Type: ApplicationFiled: March 15, 2018Publication date: July 19, 2018Applicant: Winbond Electronics Corp.Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
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Patent number: 9972631Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.Type: GrantFiled: November 16, 2016Date of Patent: May 15, 2018Assignee: Winbond Electronics Corp.Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
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Publication number: 20180047737Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.Type: ApplicationFiled: November 16, 2016Publication date: February 15, 2018Applicant: Winbond Electronics Corp.Inventors: Che-Fu Chuang, Hsiu-Han Liao, Yao-Ting Tsai
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Patent number: 9812641Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.Type: GrantFiled: September 29, 2014Date of Patent: November 7, 2017Assignee: Winbond Electronics Corp.Inventors: Hsiu-Han Liao, Ting-Ying Shen
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Patent number: 9356235Abstract: Structures and formation methods of memory devices are provided. The memory device includes a first electrode, a second electrode, and a resistive layer positioned between the first electrode and the second electrode. The resistive layer has a crystalline portion. A volume ratio of the crystalline portion to the resistive layer is in a range from about 0.2 to about 1.Type: GrantFiled: September 2, 2014Date of Patent: May 31, 2016Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Hsiu-Han Liao, Shuo-Che Chang, Chia Hua Ho
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Patent number: 9166160Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.Type: GrantFiled: September 10, 2014Date of Patent: October 20, 2015Assignee: Winbond Electronics Corp.Inventors: Chia-Hua Ho, Shuo-Che Chang, Hsiu-Han Liao, Po-Yen Hsu, Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Publication number: 20150287914Abstract: Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.Type: ApplicationFiled: September 10, 2014Publication date: October 8, 2015Inventors: Chia-Hua Ho, Shuo-Che Chang, Hsiu-Han Liao, Po-Yen Hsu, Meng-Hung Lin, Bo-Lun Wu, Ting-Ying Shen
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Publication number: 20150280121Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.Type: ApplicationFiled: September 29, 2014Publication date: October 1, 2015Inventors: Hsiu-Han LIAO, Ting-Ying SHEN
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Publication number: 20150280119Abstract: Structures and formation methods of memory devices are provided. The memory device includes a first electrode, a second electrode, and a resistive layer positioned between the first electrode and the second electrode. The resistive layer has a crystalline portion. A volume ratio of the crystalline portion to the resistive layer is in a range from about 0.2 to about 1.Type: ApplicationFiled: September 2, 2014Publication date: October 1, 2015Inventors: Po-Yen HSU, Hsiu-Han LIAO, Shuo-Che CHANG, Chia Hua HO