Abstract: A stereoscopic display system and a control method of the stereoscopic display system are provided. A rotation device is controlled to rotate at 2n times an image input frequency, so that the rotation device respectively completes n rotations during a period in which stereoscopic glasses receive a left-eye image and a period in which the stereoscopic glasses receive a right-eye image.

Abstract: A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

Abstract: An electronic device and an image processing method thereof are provided. The image processing method includes the following steps: detecting whether a buffer has second image data when performing a first compositing operation of first image data; detecting whether an image capturing operation of third image data is performed; judging a first time point for obtaining the third image data; and comparing a second time point for completing the first compositing operation to the first time point and determining whether to perform a second compositing operation of the second image data first or a third compositing operation of the third image data first.

Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Abstract: An improved leak-proof heat dissipation structure of high thermal conductivity materials includes an insulating film layer, a high thermal conductivity thermal interface material layer, a first flexible material composite layer, a second flexible material composite layer and a radiator. The insulating film layer has a film opening at the center. The high thermal conductivity thermal interface material layer has its body close to the heat source and located above the chip body. The first flexible material composite layer is set above the insulating film layer, and has a first opening at the center. The second flexible material composite layer is provided below the insulating film layer, and has a second opening at the center. The radiator is placed on the first flexible material composite layer, and has a boss at the bottom and multiple storage grooves on the boss.

Abstract: Provided is a method of accurate and sensitive characterization and prognosis of prostate cancer in a subject. The method includes obtaining a biological sample from the subject and determining the level of identified biomarkers.

Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) providing a first layout including a plurality of cells placed therein; (b) generating a second layout by performing a first set of calculations on the first layout such that cell congestions in the first layout is eliminated from the second layout; (c) generating a third layout by performing a second set of calculations on the second layout such that the total wire length of the third layout is less than that of the second layout; and (d) iterating the operations (b) and (c) until a target layout conforming a convergence criterion.

Abstract: Aspects of the invention include techniques for improving the accuracy of access-limited neural network inference in low-voltage regimes. A non-limiting example method includes training a first machine learning model to perform input transformation for reducing low-voltage bit errors for a deep neural network operating in a low-voltage regime. The training includes inputting training data into the first machine learning model such that, in response, the first machine learning model produces transformed training data; inputting the transformed training data into a clean machine learning model and into perturbed machine learning models, the perturbed machine learning models being generated by applying random bit errors to the clean machine learning model; and optimizing the first machine learning model based on a comparison of output of the clean machine learning model and of the perturbed machine learning models compared to groundtruth labels for the training data.

Abstract: A solar cell module and method for manufacturing the same are disclosed. The solar cell module includes a first unit and a second unit. The first unit includes a first solar cell and a first protection element. The first solar cell and the first protection element are electrically coupled in parallel with each other. The second unit includes a second solar cell and a second protection element. The second solar cell and the second protection element are electrically coupled in parallel. The first unit is electrically connected to the second unit.

Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions; forming first to fifth gate electrodes, the second gate electrode being between the first and third gate electrodes, the fourth gate electrode being between the third and fifth gate electrodes; and selectively replacing at least one portion of at least one of the gate electrodes with an isolation dummy gate, including: replacing the first and fifth gate electrodes with first and second isolation dummy gates formed in trenches through the first and second active regions; and replacing a first portion of the third gate electrode overlying the second active region with a third isolation dummy gate formed in a first trench through the second active region, resulting in a second portion of the third gate over the first active region, and the third isolation dummy gate aligned with the second portion of the third gate.

Abstract: A method for cleaning semiconductor process equipment and a system thereof are provided. The method is adapted to apply to an object with at least one pollutant thereon and includes steps of providing multi-channel optical tweezers to irradiate the pollutant and locations where the pollutant is neighbor to, in order to let the optical tweezers generate a resultant force to the pollutant; and providing an airflow to the object. The resultant force is greater than a maximum static friction between the pollutant and the object so as to remove the pollutant.

Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

Abstract: An antenna module includes two antenna units, two isolation members, and a grounding member. Each antenna unit consists of two feeding ends, two first radiators, and two second radiators. The isolating members are disposed between the first and second portions of each antenna unit. The grounding member is disposed beside the two antenna units and the two isolation members. A first slot is formed among each first radiator, the second radiator, and the grounding member. The two second radiators are connected to the third radiator. A third slot is formed between the second radiator and the second portion. The two antenna units are symmetric to the fourth slot in a mirrored manner, and the two first portions have widths gradually changing along an extending direction of the fourth position.

Abstract: A method for inspecting particles is suitable for inspecting particles on a substrate. The method for inspecting the particles includes the following. The substrate is disposed on a stage. An inspection radiation is provided to irradiate on the substrate, in which the inspection radiation is suitable for exciting the particles on the substrate to emit a secondary radiation. Also, the secondary radiation is detected to confirm whether the particles exist on the substrate and positions of the particles are detected.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Abstract: A topical formulation comprising (a) a therapeutically effective amount of tofacitinib; (b) at least one solvent; and (c) optionally one or more other pharmaceutically acceptable excipients is provided. Also provided is a method for treating and/or preventing autoimmune diseases in a subject administering said topical formulation.