Patents by Inventor Hsiung Chen

Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240052577
    Abstract: A forming machine for a pulp product includes a frame unit defining a forming zone, two hot pressing zones, and two demolding zones; a forming unit disposed in the forming zone and including a forming mold for scooping pulp from a pulp tank and forming a blank unit thereon for every scoop of the pulp; a lower mold unit including four lower molds movable relative to the frame unit along a vertical direction, and an upper mold unit movable between two positions along a moving direction in a repetitive manner and including two upper hot-pressing central molds and two upper hot-pressing transfer molds. The upper mold unit is engageable with the forming mold and a corresponding one of the lower molds in different positions.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 15, 2024
    Inventors: Chun-Hsiung CHEN, Kao-Yi CHANG
  • Publication number: 20240032660
    Abstract: A lighting umbrella having a main body, a lighting device and a reflector; the lighting device and the reflector both cooperate with an upper part of the main body and are both provided at an inner side of the canopy of the main body; the reflector reflects light emitted by the lighting device to an area under the main body. It effectively increases the lighting area of the road surface, so that it is easier for users to check road conditions in an environment without sufficient light. It can also prevent the light emitted by the lighting device from causing discomfort to the eyes of the people facing thereto.
    Type: Application
    Filed: April 28, 2023
    Publication date: February 1, 2024
    Inventors: Sun Jung CHEN, Sun Feng SUNG, Ming Hsiung CHEN
  • Publication number: 20240020457
    Abstract: A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Po-Hsiang HUANG
  • Publication number: 20240020451
    Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
  • Publication number: 20240007283
    Abstract: A cryptographic device for a memory device includes a determination unit, a mapping unit, and a cryptographic unit. The determination unit determines that a memory address is in a protection area to select a key and a random number. The mapping unit maps a binary code to an injection code according to the key and the memory address, in which the binary code includes the random number and the memory address. The cryptographic unit generates a key stream according to the key and the injection code.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 4, 2024
    Inventors: Shun-Hsiung CHEN, Kun-Yi WU, Yu-Shan LI
  • Patent number: 11861284
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Patent number: 11861282
    Abstract: A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu
  • Patent number: 11860545
    Abstract: An exposure device includes a laser source, a first spatial light modulator, a second spatial light modulator and a controller. The laser source is provided for emitting a laser. The first spatial light modulator is irradiated by the laser and used for modulating the phase of the laser irradiated on the first spatial light modulator before reflecting the laser. The second spatial light modulator is irradiated by the laser reflected from the first spatial light modulator and used for modulating the amplitude of the laser irradiated on the second spatial light modulator before reflecting the laser. The laser reflected by the second spatial light modulator is irradiated on a photoresist layer to form an exposure pattern.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: January 2, 2024
    Inventors: Chun-Jung Chiu, Chun-Hsiung Chen, Wan-Chen Chuang
  • Patent number: 11854978
    Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Patent number: 11855632
    Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen, Kuo-Nan Yang
  • Publication number: 20230403205
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for quality prediction. The method includes obtaining values of a parameter of a first endpoint, obtaining values of a parameter of a second endpoint, and generating a prediction of the parameter of the first endpoint according to the values of the parameter of the first endpoint and the values of the parameter of the second endpoint. The prediction includes probability distribution information of the parameter of the first endpoint at a timing in the future. The present disclosure can result in a more precise quality prediction.
    Type: Application
    Filed: September 9, 2022
    Publication date: December 14, 2023
    Inventors: Li-Han CHEN, Jin-Wei LIU, Yi-Hsiung CHEN, Yung-Chi HSU
  • Patent number: 11841944
    Abstract: A parameter checking method includes substituting a plurality of initial parameters into a data integrity algorithm to obtain syndrome data using a processor, and using a hardware cipher to calculate a calculation result based on the data integrity algorithm based on a plurality of calculation parameters corresponding to the initial parameters. Moreover, when the processor determines that the syndrome data is not the same as the calculation result, the processor outputs a hacker attack message, indicating that at least one of the calculation parameters has been tampered with.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: December 12, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Shun-Hsiung Chen
  • Patent number: 11835363
    Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: December 5, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Chung Chen, Hsun-Wei Chan, Lu-Ming Lai, Kuang-Hsiung Chen
  • Publication number: 20230371665
    Abstract: A power supply control structure of an umbrella, having an umbrella body and a power supply device, the umbrella body has a shaft, a notch at the upper end of the shaft, a runner movably sleeving the shaft, and a rib assembly hinged with the notch and the runner; the power supply device is positioned on an upper part of the umbrella body. Accordingly, a conductive connecting piece for connecting the power supply device and an electronic device on the upper part of the umbrella body is minimally limited by the shaft so that installation position of the conductive connecting piece can be simpler and more convenient.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Inventors: Sun Jung CHEN, Sun Feng Sung, Ming Hsiung Chen
  • Publication number: 20230376661
    Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chi-Lin LIU, Jerry Chang-Jui KAO, Wei-Hsiang MA, Lee-Chung LU, Fong-Yuan CHANG, Sheng-Hsiung CHEN, Shang-Chih HSIEH
  • Patent number: 11821145
    Abstract: A pulp mold includes a mold main body extending along a longitudinal axis and having an inner surface that defines a chamber, an outer surface opposite to the inner surface, and a plurality of channel grooves extending inwardly from the outer surface toward the inner surface and extending along a length of the outer surface. The chamber is divided into a plurality of chamber sections decreasing in diameters gradually and upwardly from the opening along the longitudinal axis. Each channel groove does not communicate with the chamber. A plurality of air holes extend from the outer surface to the inner surface, pass through the channel grooves, and communicate the chamber with the outside.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: November 21, 2023
    Assignee: Yulan Green Technology Co., Ltd.
    Inventors: Chun-Hsiung Chen, Kao-Yi Chang
  • Publication number: 20230359799
    Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Limited
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Publication number: 20230356890
    Abstract: A container has a main body assembly, a top cover, and a top cover open-close operating unit. The main body assembly has a base and a sleeving cylinder. The sleeving cylinder rotatably sleeves the base and has an accommodating space with an opening upward and being capable of accommodating a content. The top cover is pivotally mounted on a top of the sleeving cylinder and is capable of opening and closing the opening of the accommodating space. The top cover open-close operating unit is moveably mounted in the main body assembly and is connected to the top cover. When the sleeving cylinder is rotated relative to the base, the sleeving cylinder drives the top cover to open or to close the opening of the accommodating space of the sleeving cylinder via the top cover open-close operating unit. The container facilitates ease in operation in opening and closing.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventor: Sin-Hsiung CHEN
  • Publication number: 20230359135
    Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark , each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
  • Publication number: 20230342532
    Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout, wherein the first layout includes a first row and a second row adjacent to the first row; (b) dividing the first layout into a plurality of regions; (c) calculating a first density of each of the plurality of regions; (d) calculating, for a first region of the plurality of regions, a first probability of altering cell versions for cells in the first region according to the first density of the first region; (e) altering cell versions of one or more cells in the first region according to a comparison between the first probability and a first threshold; and (f) rearranging the cells in the first layout to reduce cell overlap.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventors: WAI-KEI MAK, TING-CHI WANG, TSU-LING HSIUNG, HSUAN-HAN LIANG, SHENG-HSIUNG CHEN