Patents by Inventor Hsiung-Shih CHANG

Hsiung-Shih CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312421
    Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.
    Type: Application
    Filed: July 22, 2019
    Publication date: October 1, 2020
    Inventors: Hsiung-Shih CHANG, Yu-Cheng LIAO, Meng-Hsueh TSAI
  • Patent number: 10347524
    Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Li-Che Chen
  • Patent number: 10056260
    Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 21, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Hsiung-Shih Chang, Pei-Heng Hung, Chia-Hao Lee, Jui-Chun Chang, Chih-Cherng Liao
  • Publication number: 20180190493
    Abstract: A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Hsiung-Shih CHANG, Pei-Heng HUNG, Chia-Hao LEE, Jui-Chun CHANG, Chih-Cherng LIAO
  • Publication number: 20180076288
    Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih CHANG, Jui-Chun CHANG, Li-Che CHEN
  • Patent number: 9773902
    Abstract: A semiconductor device including a substrate having an active region and a field-plate region therein is disclosed. At least one trench-gate structure is in the substrate. The field-plate region is at a first side of the trench-gate structure. At least one source doped region is in the substrate at a second side opposite to the first side of the trench-gate structure. The source doped region adjoins the sidewall of the trench-gate structure. A drain doped region is in the substrate corresponding to the active region. The field-plate region is between the drain doped region and the trench-gate structure. An extending direction of length of the trench-gate structure is perpendicular to that of the drain doped region as viewed from a top-view perspective.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 26, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chun Chang, Hsiung-Shih Chang
  • Patent number: 9666485
    Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 30, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang, Hsiung-Shih Chang
  • Patent number: 9666699
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 30, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jun-Wei Chen
  • Patent number: 9646964
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 9, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Pei-Heng Hung, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9607944
    Abstract: A semiconductor device includes a plurality of first wires and second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center, and each of the second wires forms the closed polygon and surrounds the center. The first and second wires are interlaced, and none of the first and second wires are coupled to each other. The first conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the first wires. The second conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the second wires. The first conductive layer is disposed between the second conductive layer and the first and second wires, and the first and second conductive layers are not coupled to each other.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 28, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Hsiung-Shih Chang, Manoj Kumar, Yen-Ni Lee, Teng-Shao Su
  • Publication number: 20170025411
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Pei-Heng HUNG, Hsiung-Shih CHANG, Chia-Hao LEE, Jui-Chun CHANG
  • Patent number: 9548375
    Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
  • Publication number: 20160379924
    Abstract: A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires is forming the closed polygon and surrounding the center. The first and second wires are interlaced, and none of the first wires and second wires are coupled to each other.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih CHANG, Pei-Heng HUNG
  • Patent number: 9530732
    Abstract: A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires is forming the closed polygon and surrounding the center. The first and second wires are interlaced, and none of the first wires and second wires are coupled to each other.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: December 27, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Pei-Heng Hung
  • Patent number: 9502584
    Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 22, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
  • Patent number: 9478644
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well region having the first conduction type is disposed in the semiconductor layer. A second well and a third well having a second conduction type are disposed to opposite sides of the first well region. The second well and the third well are separated from the first well region. A first anode doped region is disposed in the second well. A second anode doped region and a third anode doped region having the first conduction type are disposed in the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Publication number: 20160300930
    Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 13, 2016
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung LEE, Jui-Chun CHANG, Hsiung-Shih CHANG
  • Patent number: 9406742
    Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: August 2, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang, Hsiung-Shih Chang
  • Patent number: 9391139
    Abstract: A top-side contact structure is provided. The top-side contact structure includes a substrate. The substrate includes a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer. The top-side contact structure also includes a first trench and a second trench formed in the second semiconductor layer and respectively extending along a first direction and a second direction. The first trench and the second trench connect to each other at an intersection point. The top-side contact structure also includes an insulating material filling the first trench and the second trench. The top-side contact structure also includes a contact plug formed at the intersection point and directly contacting the first semiconductor layer. A method for fabricating a top-side contact structure is also provided.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 12, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Li-Che Chen
  • Patent number: 9390983
    Abstract: A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 12, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Chih-Jen Huang