Patents by Inventor Hsu-Nan FANG
Hsu-Nan FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369154Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Hsu-Nan FANG
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Patent number: 11791434Abstract: An electronic package is provided. The electronic package includes a carrier, a first electronic component, a bonding element, and a barrier. The carrier has a conductive layer. The first electronic component is disposed adjacent to the carrier and has a first terminal and a second terminal. The bonding element is configured to electrically connect the conductive layer to the first terminal. The barrier is configured to avoid electrically bypassing an electrical path in the first electronic component and between the first terminal and the second terminal.Type: GrantFiled: November 9, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jun-Wei Chen, Yu-Yuan Yeh, Hsu-Nan Fang
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Patent number: 11710675Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.Type: GrantFiled: February 17, 2021Date of Patent: July 25, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Publication number: 20230223352Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Publication number: 20230144000Abstract: An electronic package is provided. The electronic package includes a carrier, a first electronic component, a bonding element, and a barrier. The carrier has a conductive layer. The first electronic component is disposed adjacent to the carrier and has a first terminal and a second terminal. The bonding element is configured to electrically connect the conductive layer to the first terminal. The barrier is configured to avoid electrically bypassing an electrical path in the first electronic component and between the first terminal and the second terminal.Type: ApplicationFiled: November 9, 2021Publication date: May 11, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jun-Wei CHEN, Yu-Yuan YEH, Hsu-Nan FANG
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Patent number: 11605597Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.Type: GrantFiled: April 17, 2020Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Publication number: 20220415799Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface. The semiconductor package structure also includes a passive component connected to the second surface of the electronic component. The semiconductor package structure further includes a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Hsu-Nan FANG
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Patent number: 11538778Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.Type: GrantFiled: December 18, 2020Date of Patent: December 27, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Publication number: 20220367369Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.Type: ApplicationFiled: August 2, 2022Publication date: November 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
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Patent number: 11502024Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first semiconductor element, a first redistribution layer, a second redistribution layer, and a conductive via. The first semiconductor element has a first active surface and a first back surface opposite to the first active surface. The first redistribution layer is disposed adjacent to the first back surface of the first semiconductor element. The second redistribution layer is disposed adjacent to the first active surface of the first semiconductor element. The conductive via is disposed between the first redistribution layer and the second redistribution layer, where the conductive via inclines inwardly from the second redistribution layer to the first redistribution layer.Type: GrantFiled: January 21, 2020Date of Patent: November 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Publication number: 20220262697Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Hsu-Nan FANG
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Patent number: 11404380Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.Type: GrantFiled: December 19, 2019Date of Patent: August 2, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Publication number: 20220199559Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Hsu-Nan FANG
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Patent number: 11316274Abstract: A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.Type: GrantFiled: June 5, 2019Date of Patent: April 26, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Nan Lin, Hsu-Nan Fang
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Patent number: 11282778Abstract: A semiconductor device package includes a redistribution structure, a conductive substrate stacked on the redistribution structure and an encapsulant encapsulating the redistribution structure and the conductive substrate. The encapsulant encapsulates a side surface of the conductive substrate. A method for manufacturing an electronic device package includes: providing a carrier, forming a redistribution structure on the carrier, mounting a conductive substrate on a first surface of the redistribution structure, forming a first encapsulant to encapsulate the first surface of the redistribution structure and a side surface of the conductive substrate, and removing the carrier.Type: GrantFiled: December 4, 2019Date of Patent: March 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Patent number: 11282772Abstract: A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other.Type: GrantFiled: November 6, 2019Date of Patent: March 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Patent number: 11276661Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.Type: GrantFiled: May 22, 2020Date of Patent: March 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Hsu-Nan Fang
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Publication number: 20220059406Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.Type: ApplicationFiled: August 21, 2020Publication date: February 24, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Hsu-Nan FANG
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Patent number: 11257788Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.Type: GrantFiled: September 24, 2019Date of Patent: February 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
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Patent number: 11257776Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.Type: GrantFiled: September 17, 2019Date of Patent: February 22, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Sheng Lin, Chin-Li Kao, Hsu-Nan Fang