Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

Abstract: A light source module and a projection device are provided. The light source module is configured to provide a laser beam and includes multiple laser source units and a focusing lens. The laser source units include a first laser source unit and a second laser source unit, respectively configured to provide a first laser beam and a second laser beam. The focusing lens is located on transmission paths of the first laser beam and the second laser beam. The first laser beam and the second laser beam are respectively incident on the focusing lens along a first direction. The first laser source unit and the second laser source unit are arranged along a second direction.

Abstract: An image processing circuit is provided. The image processing circuit includes a dither computing circuit and a blending circuit. The dither computing circuit performs a dither computing on the input grayscale data to generate a dithered grayscale data. The blending circuit receives the input grayscale data and the dithered grayscale data, generates a blending weight by comparing the input grayscale data with a first threshold, and performs a blending computing on the input grayscale data and the dithered grayscale data based on the blending weight to output an output grayscale data.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.

Abstract: The state of protein phosphorylation and glycosylation can be key determinants of cellular physiology such as early stage cancer, but the development of phosphoproteins and/or glycoproteins in biofluids for disease diagnosis remains elusive. Here we demonstrate, for the first time, a strategy to isolate and identify phosphoproteins/glycoproteins in extracellular vesicles (EVs) from human plasma as potential markers to differentiate disease from healthy states. We identified close to 10,000 unique phosphopeptides in EVs by isolating from small volume of plasma samples. Using label-free quantitative phosphoproteomics, we identified 144 phosphoproteins in plasma EVs that are significantly higher in patients diagnosed with breast cancer than in healthy controls. Several novel biomarkers were validated in individual patients using Paralleled Reaction Monitoring for targeted quantitation. Similarly a group of glycoproteins in plasma EVs are identified.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: A light source module and a projection device are provided. The light source module is configured to provide a laser beam and includes multiple laser source units and a focusing lens. The laser source units include a first laser source unit, a second laser source unit, a third laser source unit and a fourth laser source unit respectively configured to provide a first laser beam, a second laser beam, a third laser beam and a fourth laser beam. The focusing lens is located on transmission paths of the first laser beam, the second laser beam, the third laser beam and the fourth laser beam. The first laser beam, the second laser beam, the third leaser beam and the fourth laser beam are respectively incident on the focusing lens along a first direction. The first laser source unit and the second laser source unit are arranged along a second direction.

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

Abstract: A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

Abstract: Aspects of the subject disclosure may include, for example, assigning a first interest measure associated with a first input to a learning machine at a first cycle, determining a first intelligence level according to a first product of the first interest measure and a first performance level based on the first input, and responsive to receiving a subsequent input at a subsequent cycle, reducing the first interest measure associated with the first input at the first cycle of the learning machine according to a total number of cycles that have occurred since the first cycle, assigning a new interest measure to the subsequent input at the subsequent cycle, generating a subsequent performance level according to the subsequent input, and determining a subsequent intelligence level according to a second product of the subsequent interest level and a subsequent performance level. Other embodiments are disclosed.

Abstract: An object displaying system includes a right light signal generator, a left light signal generator, a right combiner, and a left combiner. The right light signal generator generates right light signals for an object. The right combiner receives and redirects the right light signals towards one retina of a viewer to display multiple right pixels of the object. The left light signal generator generates leftght signals for the object. The left combiner receives and redirects the left light signals towards the other retina of the viewer to display multiple left pixels of the object. A first redirected right light signal and a corresponding first redirected left light signal are perceived by the viewer to display a first virtual binocular pixel of the object with a first depth that is related to a first angle between the first redirected right light signal and the corresponding first redirected left light signal.

Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a carrier member and an image sensor. The carrier member has a light holder, a lens holder, an accommodation space and a tilted wall. The first light source is arranged on the light holder of the carrier member, and reflected light associated with the first light source penetrates through the lens to propagate to the image sensor inside the accommodation space. Reflected light associated with the second light source penetrates through the tilted wall of the carrier member to propagate to the image sensor.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.