Abstract: A semiconductor structure includes a channel structure, a gate structure, two source/drain features, and a plurality of inner spacers. The channel structure includes a plurality of channel features which are spaced apart from each other. The gate structure is disposed to surround the channel features. The source/drain features are disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. Each of the inner spacers is disposed to separate the gate structure from a corresponding one of the source/drain features. Each of the inner spacers includes an inner spacer body and a lateral nitrided portion. The lateral nitrided portion is in direct contact with the corresponding one of the source/drain features and has a nitrogen content greater than that of the inner spacer body.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a first FET, and a second FET. The first FET includes first and second fin structures disposed on first and second fin bases, respectively, a first S/D region disposed on the first and second fin bases and in contact with side surfaces of the first and second fin structures, and a first pair of spacers disposed on opposite sidewalls of the first S/D region. The second FET includes third and fourth fin structures disposed on third and fourth fin bases, respectively, a second S/D region disposed on the third and fourth fin structures, and a second pair of spacers disposed on opposite sidewalls of the second S/D region. A height of the first pair of spacers is greater than a height of the second pair of spacers.

Abstract: h A method for using a trained machine learning model to predict risk of incident opioid use disorder (OUD) and/or of N an opioid overdose episode for a subject. The method comprises using at least one computer hardware processor to perform: accessing data associated with the subject, wherein the data comprises values for a plurality of predictors; generating input features for the trained machine learning model from the data; and providing the input features as input to the trained machine learning model to obtain an output indicative of the risk of OUD and/or of the opioid overdose episode for the subject, wherein the trained machine learning model comprises a first plurality of values for a respective first plurality of parameters, the first plurality of values used by the at least one computer hardware processor to obtain the output from the input features.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a one or more drones includes a radio-frequency (RF) receiver configured to receive an RF signal transmitted between a drone and a controller. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, the set of samples comprising samples of the first RF signal, obtain a parameter model of the first frequency hopping parameters, and fit the parameter model to the set of samples.

Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.

Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.

Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a drone includes a radio-frequency (RF) receiver. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, obtain predetermined data of expected communication protocols used between the drone and a controller, and determine whether the RF signal corresponds to one of the expected communication protocols by comparing the samples of the RF signal to the predetermined data and decoding the RF signal. In further aspects the system extracts a unique identifier of the drone based at least partially on the decoded RF signal.

Abstract: A high voltage device includes: a semiconductor layer, a well, a drift oxide region, a body region, a gate, a source, a drain, and a field plate. The well has a first conductivity type, and is formed in a semiconductor layer. The drift oxide region is formed on the semiconductor layer. The body region has a second conductivity type, and is formed in the semiconductor layer, wherein the body region and a drift region are connected in a channel direction. The gate is formed on the semiconductor layer. The source and the drain have the first conductivity type, and are formed in the semiconductor layer, wherein the source and the drain are in the body region and the well, respectively. The field plate is formed on and connected with the drift oxide region, wherein the field plate is electrically conductive and has a temperature coefficient (TC) not higher than 4 ohm/° C.

Abstract: A system and method for detecting a scrambling seed in communication between a drone and a controller are described. The system comprises a radio-frequency (RF) receiver configured to receive an RF signal transmitted between the drone and a controller. The RF signal includes scrambled data that contain repetitions of unscrambled data based on known scramblers with an unknown scrambling seed. The system further comprises a memory device in communication with a hardware processor and having stored computer-executable instructions to cause the hardware processor to identify the smallest number of bits required in each segment of scrambled data for data combining by finding an invertible predetermined matrix. The hardware processor is configured to determine the unknown scrambling seed based on a function combining the predetermined matrix, transition matrices of scramblers, and segments of received scrambled data.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a drone includes a radio-frequency (RF) receiver. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, obtain predetermined data of expected communication protocols used between the drone and a controller, and determine whether the RF signal corresponds to one of the expected communication protocols by comparing the samples of the RF signal to the predetermined data and decoding the RF signal. In further aspects the system extracts a unique identifier of the drone based at least partially on the decoded RF signal.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a one or more drones includes a radio-frequency (RF) receiver configured to receive an RF signal transmitted between a drone and a controller. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, the set of samples comprising samples of the first RF signal, obtain a parameter model of the first frequency hopping parameters, and fit the parameter model to the set of samples.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: A system and method for detecting a scrambling seed in communication between a drone and a controller are described. The system comprises a radio-frequency (RF) receiver configured to receive an RF signal transmitted between the drone and a controller. The RF signal includes scrambled data that contain repetitions of unscrambled data based on known scramblers with an unknown scrambling seed. The system further comprises a memory device in communication with a hardware processor and having stored computer-executable instructions to cause the hardware processor to identify the smallest number of bits required in each segment of scrambled data for data combining by finding an invertible predetermined matrix. The hardware processor is configured to determine the unknown scrambling seed based on a function combining the predetermined matrix, transition matrices of scramblers, and segments of received scrambled data.