Abstract: A method that reorders partitioning candidates or motion vectors based on template matching costs for geometric prediction mode (GPM) is provided. A video coder receives data to be encoded or decoded as a current block of a current picture of a video. The current block is partitioned into first and second partitions by a bisecting line defined by an angle-distance pair. The video coder identifies a list of candidate prediction modes for coding the first and second partitions. The video coder computes a template matching (TM) cost for each candidate prediction mode in the list. The video coder receives or signals a selection of a candidate prediction mode based on an index that is assigned to the selected candidate prediction mode based on the computed TM costs. The video coder reconstructs the current block by using the selected candidate prediction mode to predict the first and second partitions.

Abstract: An improved integrated coil structure includes an iron core body and first, second, third, and fourth coils. The iron core body includes first and second wire-winding portions. The iron core body is provided with first and second flanges respectively at two sides thereof and a third flange arranged between the first and second flanges. First and second electrodes are arranged on the first flange. Third and fourth electrodes are arranged on the second flange. Fifth, sixth, and seventh electrodes are arranged on the third flange. Two terminals of the first coil are electrically connected with the first and fifth electrodes. Two terminals of the second coil are electrically connected with the second and seventh electrodes. Two terminals of the third coil are electrically connected with the third and sixth electrodes. Two terminals of the fourth coil are electrically connected with the fourth and seventh electrodes.

Abstract: The network transformer includes an iron core body, and first, second, and third winding assemblies. The iron core body has first and second winding sections. A first flange and a second flange are on both ends of the iron core body, and a third flange situated between the first and second flanges. The first winding section is positioned between the first and third flange s, while the second winding section is located between the second and third flanges. The first, second, and third flanges respectively have first, second, and third electrode sets. The two ends of the coils in the first winding assembly are electrically connected to the first electrode set. The second winding assembly has the two ends of the coils electrically connected to the third electrode set. The third winding assembly has the two ends of the coils electrically connected to the second and third electrode sets.

Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

Abstract: An integrated coil module includes: a substrate; a plurality of inductor elements arranged on the substrate with a spacing distance between adjacent inductor elements, the inductor elements each including an iron core, first and second coils wound on the iron core, first and second flanges at two sides of the iron core, and a third flange arranged on the iron core and between the first and second flanges, the first flange including first and second electrodes, the second flange including third and fourth electrodes, the third flange including fifth and sixth electrodes; and a plate arranged atop the plurality of inductor elements to cover the inductor elements. As such, the plurality of inductor elements are integrated together as a one-piece structure to thereby simplify the SMT manufacturing process and shorten the spacing distance between the inductor elements so as to reduce the area of the substrate occupied thereby.

Abstract: A package structure is provided, and includes a first bonding film formed on a first substrate, and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film formed on a second substrate and bonded to the first bonding film, and a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other. In a top view, the first alignment mark is spaced apart from the second alignment mark, and the distance between adjacent first patterns is less than the distance between the first alignment mark and the second alignment mark.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a transistor layer over a substrate and forming a trench in the transistor layer. A depth to width ratio of the trench is greater than or equal to 3. The method further includes filling the trench with a gap-fill material using a flowable chemical vapor deposition process, wherein a precursor and a reactant are used in the flowable chemical vapor deposition process, and a ratio of the precursor to the reactant is about 1.

Abstract: The capacitor-type network transformer includes a circuit board, at least one a transformer member mounted to the circuit board, at least one peripheral element mounted to the circuit board to a side of the transformer member, and a casing configured on the circuit board completely covering the transformer members and the peripheral elements. Each transformer member includes a transformer, a common-mode filter, and at least one capacitor. The present invention configures at least a transformer member and at least a peripheral element on a circuit board through Surface Mount Technology (SMT), which are all entirely covered by a casing, thereby avoiding the conventional manual process's complexity and inconvenience, and enhancing production cost and efficiency. As the peripheral elements, such as Transient Voltage Suppressor (TVS) diodes, are also integrated inside the casing, the network transformer is more robust to electrical shocks and easier for product miniaturization.

Abstract: The inductor-type network transformer includes a circuit board, at least one transformer member mounted to the circuit board, at least one peripheral element mounted to the circuit board to a side of the transformer member, and a casing configured on the circuit board completely covering the at least one transformer member, and the at least one peripheral element. The present invention configures at least a transformer member and at least a peripheral element on a circuit board through Surface Mount Technology (SMT), which are all entirely covered by a casing, thereby avoiding the conventional manual process's complexity and inconvenience, and enhancing production cost and efficiency. As the peripheral elements, such as Transient Voltage Suppressor (TVS) diodes, are also integrated inside the casing, the network transformer is more robust to electrical shocks. The integration of the peripheral elements inside the casing also helps to product miniaturization.

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

Abstract: Systems and methods for providing drone activity cloud services to cloud consumers using cloud and edge computing are provided. The drone monitoring service is rendered by drone sensors detecting and identifying drones, cloud and edge servers aggregating drone activity data from sensors and UAS traffic management systems, and cloud consumers monitoring drone activities using cloud and edge devices to access the cloud. The drone data analytics service reports drone activity statistics, predicted drone activities, and abnormal behaviors to cloud consumers based on the statistics and behavior models obtained by machine learning and federated learning techniques. The drone mitigation service, when initiated by cloud consumers, determines how to optimally configure sensors and collaboratively send signals to deactivate unauthorized drones. Moreover, data processing, artificial intelligence, mobility support, and traffic management functional units empower cloud and edge servers to support these cloud services.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a drone includes a radio-frequency (RF) receiver. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, obtain predetermined data of expected communication protocols used between the drone and a controller, and determine whether the RF signal corresponds to one of the expected communication protocols by comparing the samples of the RF signal to the predetermined data and decoding the RF signal. In further aspects the system extracts a unique identifier of the drone based at least partially on the decoded RF signal.

Abstract: A semiconductor structure includes a channel structure, a gate structure, two source/drain features, and a plurality of inner spacers. The channel structure includes a plurality of channel features which are spaced apart from each other. The gate structure is disposed to surround the channel features. The source/drain features are disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. Each of the inner spacers is disposed to separate the gate structure from a corresponding one of the source/drain features. Each of the inner spacers includes an inner spacer body and a lateral nitrided portion. The lateral nitrided portion is in direct contact with the corresponding one of the source/drain features and has a nitrogen content greater than that of the inner spacer body.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a first FET, and a second FET. The first FET includes first and second fin structures disposed on first and second fin bases, respectively, a first S/D region disposed on the first and second fin bases and in contact with side surfaces of the first and second fin structures, and a first pair of spacers disposed on opposite sidewalls of the first S/D region. The second FET includes third and fourth fin structures disposed on third and fourth fin bases, respectively, a second S/D region disposed on the third and fourth fin structures, and a second pair of spacers disposed on opposite sidewalls of the second S/D region. A height of the first pair of spacers is greater than a height of the second pair of spacers.

Abstract: h A method for using a trained machine learning model to predict risk of incident opioid use disorder (OUD) and/or of N an opioid overdose episode for a subject. The method comprises using at least one computer hardware processor to perform: accessing data associated with the subject, wherein the data comprises values for a plurality of predictors; generating input features for the trained machine learning model from the data; and providing the input features as input to the trained machine learning model to obtain an output indicative of the risk of OUD and/or of the opioid overdose episode for the subject, wherein the trained machine learning model comprises a first plurality of values for a respective first plurality of parameters, the first plurality of values used by the at least one computer hardware processor to obtain the output from the input features.

Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.

Abstract: Systems and methods for detecting, monitoring, and mitigating the presence of a drone are provided herein. In one aspect, a system for detecting presence of a one or more drones includes a radio-frequency (RF) receiver configured to receive an RF signal transmitted between a drone and a controller. The system can further include a processor and a computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the at least one processor to receive a set of samples from the RF receiver for a time interval, the set of samples comprising samples of the first RF signal, obtain a parameter model of the first frequency hopping parameters, and fit the parameter model to the set of samples.

Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.